_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity vfft32_and_a_b_v2_0 is
    port(
        a_in            : in     vl_logic;
        b_in            : in     vl_logic;
        and_out         : out    vl_logic
    );
end vfft32_and_a_b_v2_0;