_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 32 行

library verilog;
use verilog.vl_types.all;
entity c_da_1d_dct_v1_0 is
    generic(
        c_clks_per_sample: integer := 8;
        c_coeff_width   : integer := 8;
        c_data_type     : integer := 0;
        c_data_width    : integer := 8;
        c_enable_rlocs  : integer := 0;
        c_enable_symmetry: integer := 0;
        c_has_reset     : integer := 0;
        c_latency       : integer := 15;
        c_operation     : integer := 0;
        c_points        : integer := 8;
        c_precision_control: integer := 0;
        c_result_width  : integer := 19;
        c_shape         : integer := 0;
        sqrt_2          : real    := 1.414214;
        c_pi            : real    := 3.141593;
        theta_bits      : integer := 64
    );
    port(
        clk             : in     vl_logic;
        din             : in     vl_logic_vector;
        dout            : out    vl_logic_vector;
        nd              : in     vl_logic;
        rdy             : out    vl_logic;
        rfd             : out    vl_logic;
        rst             : in     vl_logic
    );
end c_da_1d_dct_v1_0;