_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 38 行

library verilog;
use verilog.vl_types.all;
entity c_gate_bit_bus_v5_0 is
    generic(
        c_ainit_val     : string  := "";
        c_enable_rlocs  : integer := 1;
        c_gate_type     : integer := 0;
        c_has_aclr      : integer := 0;
        c_has_ainit     : integer := 0;
        c_has_aset      : integer := 0;
        c_has_ce        : integer := 0;
        c_has_o         : integer := 0;
        c_has_q         : integer := 1;
        c_has_sclr      : integer := 0;
        c_has_sinit     : integer := 0;
        c_has_sset      : integer := 0;
        c_input_inv_mask: string  := "";
        c_sinit_val     : string  := "";
        c_sync_enable   : integer := 0;
        c_sync_priority : integer := 1;
        c_width         : integer := 16
    );
    port(
        i               : in     vl_logic_vector;
        ctrl            : in     vl_logic;
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        aclr            : in     vl_logic;
        aset            : in     vl_logic;
        ainit           : in     vl_logic;
        sclr            : in     vl_logic;
        sset            : in     vl_logic;
        sinit           : in     vl_logic;
        o               : out    vl_logic_vector;
        q               : out    vl_logic_vector
    );
end c_gate_bit_bus_v5_0;