_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity dvunit_ver is
    generic(
        c_load_type     : integer := 0;
        c_size          : integer := 8
    );
    port(
        load            : in     vl_logic;
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        ainit           : in     vl_logic;
        sinit           : in     vl_logic;
        new_seed        : out    vl_logic;
        data_valid      : out    vl_logic
    );
end dvunit_ver;