_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 36 行

library verilog;
use verilog.vl_types.all;
entity mac_control_v1_0_v is
    generic(
        c_a_width       : integer := 1;
        c_b_mode        : integer := 0;
        c_b_width       : integer := 1;
        c_count_width   : integer := 1;
        c_enable_rlocs  : integer := 1;
        c_has_aclr      : integer := 0;
        c_has_ce        : integer := 0;
        c_has_count     : integer := 0;
        c_has_inreg     : integer := 0;
        c_has_rdy       : integer := 0;
        c_has_rffd      : integer := 0;
        c_has_sclr      : integer := 0;
        c_output_hold   : integer := 0;
        c_mac_count     : integer := 0;
        c_pipe_level    : string  := "";
        c_sync_enable   : integer := 0;
        fixed_count_width: integer := 31
    );
    port(
        clk             : in     vl_logic;
        count           : in     vl_logic_vector;
        bypass          : in     vl_logic;
        bypass_int      : in     vl_logic;
        load            : in     vl_logic;
        ce              : in     vl_logic;
        aclr            : in     vl_logic;
        sclr            : in     vl_logic;
        rffd            : out    vl_logic;
        rdy_del         : out    vl_logic
    );
end mac_control_v1_0_v;