_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity x_rams16 is
    generic(
        init            : integer := 0
    );
    port(
        o               : out    vl_logic;
        i               : in     vl_logic;
        clk             : in     vl_logic;
        we              : in     vl_logic;
        adr0            : in     vl_logic;
        adr1            : in     vl_logic;
        adr2            : in     vl_logic;
        adr3            : in     vl_logic
    );
end x_rams16;