_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity x_or7 is
    port(
        o               : out    vl_logic;
        i0              : in     vl_logic;
        i1              : in     vl_logic;
        i2              : in     vl_logic;
        i3              : in     vl_logic;
        i4              : in     vl_logic;
        i5              : in     vl_logic;
        i6              : in     vl_logic
    );
end x_or7;