_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity ifddrrse is
    port(
        q0              : out    vl_logic;
        q1              : out    vl_logic;
        c0              : in     vl_logic;
        c1              : in     vl_logic;
        ce              : in     vl_logic;
        d               : in     vl_logic;
        r               : in     vl_logic;
        s               : in     vl_logic
    );
end ifddrrse;