_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 20 行

library verilog;
use verilog.vl_types.all;
entity bscan is
    generic(
        cds_action      : string  := "ignore"
    );
    port(
        drck            : out    vl_logic;
        idle            : out    vl_logic;
        sel1            : out    vl_logic;
        sel2            : out    vl_logic;
        tdo             : out    vl_logic;
        tck             : in     vl_logic;
        tdi             : in     vl_logic;
        tdo1            : in     vl_logic;
        tdo2            : in     vl_logic;
        tms             : in     vl_logic
    );
end bscan;