_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 26 行

library verilog;
use verilog.vl_types.all;
entity cy4 is
    generic(
        cds_action      : string  := "ignore"
    );
    port(
        cout            : out    vl_logic;
        cout0           : out    vl_logic;
        a0              : in     vl_logic;
        a1              : in     vl_logic;
        add             : in     vl_logic;
        b0              : in     vl_logic;
        b1              : in     vl_logic;
        c0              : in     vl_logic;
        c1              : in     vl_logic;
        c2              : in     vl_logic;
        c3              : in     vl_logic;
        c4              : in     vl_logic;
        c5              : in     vl_logic;
        c6              : in     vl_logic;
        c7              : in     vl_logic;
        cin             : in     vl_logic
    );
end cy4;