_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity ofddrtcpe is
    port(
        o               : out    vl_logic;
        c0              : in     vl_logic;
        c1              : in     vl_logic;
        ce              : in     vl_logic;
        clr             : in     vl_logic;
        d0              : in     vl_logic;
        d1              : in     vl_logic;
        pre             : in     vl_logic;
        t               : in     vl_logic
    );
end ofddrtcpe;