_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 24 行

library verilog;
use verilog.vl_types.all;
entity decode16 is
    port(
        o               : out    vl_logic;
        a0              : in     vl_logic;
        a1              : in     vl_logic;
        a2              : in     vl_logic;
        a3              : in     vl_logic;
        a4              : in     vl_logic;
        a5              : in     vl_logic;
        a6              : in     vl_logic;
        a7              : in     vl_logic;
        a8              : in     vl_logic;
        a9              : in     vl_logic;
        a10             : in     vl_logic;
        a11             : in     vl_logic;
        a12             : in     vl_logic;
        a13             : in     vl_logic;
        a14             : in     vl_logic;
        a15             : in     vl_logic
    );
end decode16;