_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity jtagppc is
    port(
        tck             : out    vl_logic;
        tdippc          : out    vl_logic;
        tms             : out    vl_logic;
        tdoppc          : in     vl_logic;
        tdotsppc        : in     vl_logic
    );
end jtagppc;