_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 46 行

library verilog;
use verilog.vl_types.all;
entity dcm is
    generic(
        clk_feedback    : string  := "1X";
        clkdv_divide    : real    := 2.000000;
        clkfx_divide    : integer := 1;
        clkfx_multiply  : integer := 4;
        clkin_divide_by_2: string  := "FALSE";
        clkout_phase_shift: string  := "NONE";
        deskew_adjust   : string  := "SYSTEM_SYNCHRONOUS";
        dfs_frequency_mode: string  := "LOW";
        dll_frequency_mode: string  := "LOW";
        dss_mode        : string  := "NONE";
        duty_cycle_correction: string  := "TRUE";
        factory_jf      : integer := 0;
        maxperclkin     : integer := 100000;
        maxperpsclk     : integer := 100000;
        maxperclkfx     : integer := 40000;
        minperclkfx     : integer := 2500;
        phase_shift     : integer := 0;
        startup_wait    : string  := "FALSE"
    );
    port(
        clkfb           : in     vl_logic;
        clkin           : in     vl_logic;
        dssen           : in     vl_logic;
        psclk           : in     vl_logic;
        psen            : in     vl_logic;
        psincdec        : in     vl_logic;
        rst             : in     vl_logic;
        clk0            : out    vl_logic;
        clk90           : out    vl_logic;
        clk180          : out    vl_logic;
        clk270          : out    vl_logic;
        clk2x           : out    vl_logic;
        clk2x180        : out    vl_logic;
        clkdv           : out    vl_logic;
        clkfx           : out    vl_logic;
        clkfx180        : out    vl_logic;
        locked          : out    vl_logic;
        psdone          : out    vl_logic;
        status          : out    vl_logic_vector(7 downto 0)
    );
end dcm;