_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity cy4_07 is
    generic(
        cds_action      : string  := "ignore"
    );
    port(
        c0              : out    vl_logic;
        c1              : out    vl_logic;
        c2              : out    vl_logic;
        c3              : out    vl_logic;
        c4              : out    vl_logic;
        c5              : out    vl_logic;
        c6              : out    vl_logic;
        c7              : out    vl_logic
    );
end cy4_07;