txunit.v

UART verilog hdl 实现

module TxUNIT(Clk, Reset, Enable, Load, TxD, TRegE, TBufE, DataO);

input Clk;
input Reset;
input Enable;
input Load;
output TxD;
output TRegE;
output TBufE;
input[7:0] DataO;

//内部信号定义
reg[7:0] TBuff;  //数据发送缓冲寄存器
reg[7:0] TReg;   //数据发送寄存器
reg[3:0] BitCnt; //发送的位计数器
reg      tmpTRegE;    //发送寄存器已空着标志标示
reg      tmpTBufE;    //发送缓冲寄存器已空着标志标示
reg      TxD;
//

always@(posedge Clk)
begin
	if(Reset==0)begin
		tmpTRegE = 1;
		tmpTBufE = 1;
		TxD = 1;
		BitCnt = 4'b0000;
	end else if(Load==1)begin
		TBuff = DataO;
		tmpTBufE = 0;
	end else if(Enable==1)begin
		if((tmpTBufE==0)&&(tmpTRegE==1))begin
			TReg = TBuff;
			tmpTBufE = 1;
			tmpTRegE = 0;
		end else if(tmpTRegE==0)begin
			case(BitCnt)
			4'b0000:begin
					TxD = 0;
					BitCnt = BitCnt + 1;
                    end
			4'b0001,
			4'b0010,
			4'b0011,
			4'b0100,
			4'b0101,
			4'b0110,
			4'b0111,
			4'b1000:begin
                    TxD = TReg[0];
				    TReg[7:0] = {1'b1,TReg[7:1]};
					BitCnt = BitCnt + 1;
			        end
			4'b1001:begin
					TxD = 1;
					TReg[7:0] = {1'b1,TReg[7:1]};
					BitCnt = 4'b0000;
					tmpTRegE = 1;
					end
			default: ;
			endcase
		end
    end
end
	assign TRegE = tmpTRegE;
	assign TBufE = tmpTBufE;
endmodule