clkunit.v

来自「UART verilog hdl 实现」· Verilog 代码 · 共 75 行

module ClkUNIT(SysClk, EnableRx, EnableTx, Reset);

input SysClk;
input Reset;
output EnableRx;
output EnableTx;

//内部信号定义
reg ClkDiv26;
reg tmpEnRx;
reg tmpEnTx;
reg[4:0] Cnt26;
reg[3:0] Cnt10;
reg[4:0] Cnt16;

//
always@(posedge SysClk)
begin
	if(Reset==0)begin
    	Cnt26 = 5'b00000;
        ClkDiv26 = 0;
    end else begin
        Cnt26 = Cnt26 + 5'b00001;
        case(Cnt26)
        	5'b11010: begin ClkDiv26 = 1;
                    Cnt26 = 5'b00000;end
            default:ClkDiv26 = 0;      
        endcase
    end        
end

always@(posedge SysClk)
begin
	if(Reset==0)begin
		Cnt10 = 4'b0000;
		tmpEnRx = 0;
	end else if(ClkDiv26==1)begin
		Cnt10 = Cnt10 + 1;
    end
    
	case(Cnt10)
		4'b1010:begin
        	tmpEnRx = 1;
			Cnt10 = 0;end
		default:tmpEnRx = 0;
    endcase
end


always@(posedge SysClk)
begin
	if(Reset==0)begin
		Cnt16 = 0;
		tmpEnTx = 0;
	end else if(tmpEnRx==1)begin
        Cnt16 = Cnt16 + 1;
    end

	case(Cnt16)
		5'b01111:begin
			tmpEnTx = 1;
            Cnt16 = Cnt16 + 1;end
		5'b10001:begin
			Cnt16 = 5'b00000;
			tmpEnTx = 0;end
        default:tmpEnTx = 0;
     endcase
end


assign EnableRx = tmpEnRx;
assign EnableTx = tmpEnTx; 

endmodule