wan_andgate.vhd

来自「此为一用VHDL编写的硬件游戏程序」· VHDL 代码 · 共 11 行

library ieee;
use ieee.std_logic_1164.all;
entity wan_andgate is
port(a,b :in std_logic;
       c :out std_logic);
end wan_andgate;
architecture behave of wan_andgate is
begin
   c<=a and b;
end behave;