addm4.vhd

来自「此为一用VHDL编写的硬件游戏程序」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addm4 is
port(clk :in std_logic;
     set :in std_logic;
     qin :in std_logic_vector(1 downto 0);
     q   :buffer std_logic_vector(1 downto 0));
end addm4;
architecture behave of addm4 is
begin
   process(clk,set)
   begin
           if(set='1')then
          q<=qin;

      elsif(rising_edge(clk))then
                    if(q="11")then
              q<="11";
           else
              q<=q+1;
         end if;
      end if;
    end process;
 end behave;