📄 u11.rpt
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17 -> * * - | - - * - | <-- /PS
22 -> * - - | - - * * | <-- /RD
20 -> - - * | - - * - | <-- SWRESET
21 -> - * - | - - * * | <-- /WE
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\cpldnew\u11.rpt
u11
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------------------- LC62 /BUFFER
| +--------------------------- LC63 /CDR
| | +------------------------- LC64 /CDW
| | | +----------------------- LC61 /DACS
| | | | +--------------------- LC51 INTRSW
| | | | | +------------------- LC50 /LCD
| | | | | | +----------------- LC49 /LEDS
| | | | | | | +--------------- LC54 /RDSW
| | | | | | | | +------------- LC53 /SWCE
| | | | | | | | | +----------- LC52 /SWITCHES
| | | | | | | | | | +--------- LC55 /UCS
| | | | | | | | | | | +------- LC57 /UOE
| | | | | | | | | | | | +----- LC58 /UWE
| | | | | | | | | | | | | +--- LC59 /WRSW
| | | | | | | | | | | | | | +- LC60 /XFER
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
Pin
16 -> - * * - * - - * * - - - - * - | - - - * | <-- A0
10 -> - * * - * * - * * - - - - * - | - - - * | <-- A1
9 -> * * * * * * * * * * * - - * * | - - - * | <-- A2
8 -> * * * * * * * * * * * - - * * | - - - * | <-- A3
5 -> - - - - - - - - - - - * * - - | - - - * | <-- A12
11 -> - - - - - - - - - - - * * - - | - - - * | <-- A13
6 -> - - - - - - - - - - * * * - - | - - - * | <-- A14
4 -> * * * * * * * * * * * * * * * | - - - * | <-- A15
18 -> * * * * * * * * * * * * * * * | - - - * | <-- /IOS
22 -> - * - - - - - * - - - * - - - | - - * * | <-- /RD
15 -> * - - - - - - - - - - - - - - | - - - * | <-- /STRB
21 -> - - * - * - - - - - - - * * - | - - * * | <-- /WE
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\cpldnew\u11.rpt
u11
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A12 : INPUT;
A13 : INPUT;
A14 : INPUT;
A15 : INPUT;
SWRESET : INPUT;
/DS : INPUT;
/IOS : INPUT;
/PS : INPUT;
/RD : INPUT;
/STRB : INPUT;
/WE : INPUT;
-- Node name is 'INTRSW'
-- Equation name is 'INTRSW', location is LC051, type is output.
INTRSW = LCELL( _EQ001 $ GND);
_EQ001 = !A0 & A1 & A2 & !A3 & !A15 & !/IOS & !/WE;
-- Node name is '/BUFFER'
-- Equation name is '/BUFFER', location is LC062, type is output.
/BUFFER = LCELL( _EQ002 $ VCC);
_EQ002 = A2 & A3 & !A15 & !/IOS & !/STRB
# !A2 & !A15 & !/IOS & !/STRB;
-- Node name is '/CDR'
-- Equation name is '/CDR', location is LC063, type is output.
/CDR = LCELL( _EQ003 $ VCC);
_EQ003 = A0 & !A1 & !A2 & A3 & !A15 & !/IOS & !/RD;
-- Node name is '/CDW'
-- Equation name is '/CDW', location is LC064, type is output.
/CDW = LCELL( _EQ004 $ VCC);
_EQ004 = A0 & !A1 & !A2 & A3 & !A15 & !/IOS & !/WE;
-- Node name is '/DACS'
-- Equation name is '/DACS', location is LC061, type is output.
/DACS = LCELL( _EQ005 $ VCC);
_EQ005 = !A2 & !A3 & !A15 & !/IOS;
-- Node name is '/LCD'
-- Equation name is '/LCD', location is LC050, type is output.
/LCD = LCELL( _EQ006 $ GND);
_EQ006 = !A1 & !A2 & A3 & !A15 & !/IOS;
-- Node name is '/LEDS'
-- Equation name is '/LEDS', location is LC049, type is output.
/LEDS = LCELL( _EQ007 $ VCC);
_EQ007 = A2 & A3 & !A15 & !/IOS;
-- Node name is '/RAMOE'
-- Equation name is '/RAMOE', location is LC033, type is output.
/RAMOE = LCELL( _EQ008 $ /RD);
_EQ008 = /DS & /PS & !/RD;
-- Node name is '/RAMWE'
-- Equation name is '/RAMWE', location is LC034, type is output.
/RAMWE = LCELL( _EQ009 $ /WE);
_EQ009 = /DS & /PS & !/WE;
-- Node name is '/RDSW'
-- Equation name is '/RDSW', location is LC054, type is output.
/RDSW = LCELL( _EQ010 $ VCC);
_EQ010 = A0 & !A1 & A2 & !A3 & !A15 & !/IOS & !/RD;
-- Node name is '/RS'
-- Equation name is '/RS', location is LC035, type is output.
/RS = LCELL(!SWRESET $ GND);
-- Node name is '/SWCE'
-- Equation name is '/SWCE', location is LC053, type is output.
/SWCE = LCELL( _EQ011 $ VCC);
_EQ011 = A0 & !A1 & A2 & !A3 & !A15 & !/IOS;
-- Node name is '/SWITCHES'
-- Equation name is '/SWITCHES', location is LC052, type is output.
/SWITCHES = LCELL( _EQ012 $ VCC);
_EQ012 = !A2 & A3 & !A15 & !/IOS;
-- Node name is '/UCS'
-- Equation name is '/UCS', location is LC055, type is output.
/UCS = LCELL( _EQ013 $ GND);
_EQ013 = !A2 & !A3 & !A14 & A15 & !/IOS;
-- Node name is '/UOE'
-- Equation name is '/UOE', location is LC057, type is output.
/UOE = LCELL( _EQ014 $ VCC);
_EQ014 = !A12 & !A13 & !A14 & A15 & !/IOS & !/RD;
-- Node name is '/UWE'
-- Equation name is '/UWE', location is LC058, type is output.
/UWE = LCELL( _EQ015 $ VCC);
_EQ015 = !A12 & !A13 & !A14 & A15 & !/IOS & !/WE;
-- Node name is '/WRSW'
-- Equation name is '/WRSW', location is LC059, type is output.
/WRSW = LCELL( _EQ016 $ VCC);
_EQ016 = A0 & !A1 & A2 & !A3 & !A15 & !/IOS & !/WE;
-- Node name is '/XFER'
-- Equation name is '/XFER', location is LC060, type is output.
/XFER = LCELL( _EQ017 $ VCC);
_EQ017 = !A2 & A3 & !A15 & !/IOS;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\cpldnew\u11.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,611K
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