receiver.vhd

串行输入信号经内部处理后

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY receiver IS
	PORT (clk  : IN  std_logic;
		sdata  : IN  std_logic;				----串行输入信号
		readn  : OUT std_logic;				----控制PC机读取数据的信号
		pdata  : OUT std_logic_vector(7 downto 0)		----并行信号输出
);
END receiver;

ARCHITECTURE des OF receiver IS
signal mmid           :std_logic;
signal midstate       :std_logic;
signal midpdata       :std_logic_vector(7 downto 0);
signal midcnt         :std_logic_vector(3 downto 0);
signal middcnt        :std_logic_vector(3 downto 0);
signal midscnt        :std_logic_vector(3 downto 0);
signal midsdata       :std_logic;
begin
A: process(clk)      ------2分频
Begin             
if(clk='1' and clk'event) then
   mmid<=not mmid;
 else
   mmid<=mmid;
end if;
end process A;

B: process(mmid,sdata)    -------串并处理部分
begin
if sdata='1' and midstate='1' then
  midstate<='0';
  midcnt<="0000";
  readn<='1';
  midpdata<="00000000";
  midscnt<="0000";
else  
  if(mmid='1' and mmid'event) then
     if midstate='0' then
         if midcnt<"1011" then
           if middcnt<="1000" then
             middcnt<=middcnt+'1';
             midscnt<=midscnt+sdata;
           else
             middcnt<="0000";
             midcnt<=midcnt+'1';
             if midcnt="1010" then
                pdata<=midpdata;
             end if;
             if midscnt<"0111" then
               midsdata<='0';
             else
               midsdata<='1';
             end if; 
           if midcnt<="1001" then
               midscnt<="0000";
               midpdata<=midpdata(6 downto 0) & midsdata;
           end if;
           end if;
        else
           midcnt<="1111";
           midstate<='1';
           readn<='0';
        end if;
     end if;
  end if;
end if;
end process B;
END des;