receiver.map.summary

来自「串行输入信号经内部处理后」· SUMMARY 代码 · 共 16 行

Flow Status : Successful - Mon Jan 16 15:17:20 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : receiver
Top-level Entity Name : receiver
Family : Stratix
Device : EP1S25F672C7
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 43
Total pins : 11
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0