receiver.tan.rpt

串行输入信号经内部处理后

+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Jan 16 15:17:56 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off receiver -c receiver --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "mmid" as buffer
Info: Clock "clk" has Internal fmax of 208.9 MHz between source register "midcnt[2]" and destination register "midpdata[7]" (period= 4.787 ns)
    Info: + Longest register to register delay is 4.570 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y22_N7; Fanout = 6; REG Node = 'midcnt[2]'
        Info: 2: + IC(0.753 ns) + CELL(0.527 ns) = 1.280 ns; Loc. = LC_X2_Y22_N5; Fanout = 2; COMB Node = 'LessThan~264'
        Info: 3: + IC(0.692 ns) + CELL(0.527 ns) = 2.499 ns; Loc. = LC_X2_Y22_N2; Fanout = 8; COMB Node = 'midpdata[0]~7'
        Info: 4: + IC(1.237 ns) + CELL(0.834 ns) = 4.570 ns; Loc. = LC_X2_Y21_N4; Fanout = 1; REG Node = 'midpdata[7]'
        Info: Total cell delay = 1.888 ns ( 41.31 % )
        Info: Total interconnect delay = 2.682 ns ( 58.69 % )
    Info: - Smallest clock skew is -0.004 ns
        Info: + Shortest clock path from clock "clk" to destination register is 8.167 ns
            Info: 1: + IC(0.000 ns) + CELL(1.490 ns) = 1.490 ns; Loc. = PIN_N8; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(1.454 ns) + CELL(0.846 ns) = 3.790 ns; Loc. = LC_X1_Y25_N2; Fanout = 32; REG Node = 'mmid'
            Info: 3: + IC(3.733 ns) + CELL(0.644 ns) = 8.167 ns; Loc. = LC_X2_Y21_N4; Fanout = 1; REG Node = 'midpdata[7]'
            Info: Total cell delay = 2.980 ns ( 36.49 % )
            Info: Total interconnect delay = 5.187 ns ( 63.51 % )
        Info: - Longest clock path from clock "clk" to source register is 8.171 ns
            Info: 1: + IC(0.000 ns) + CELL(1.490 ns) = 1.490 ns; Loc. = PIN_N8; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(1.454 ns) + CELL(0.846 ns) = 3.790 ns; Loc. = LC_X1_Y25_N2; Fanout = 32; REG Node = 'mmid'
            Info: 3: + IC(3.737 ns) + CELL(0.644 ns) = 8.171 ns; Loc. = LC_X1_Y22_N7; Fanout = 6; REG Node = 'midcnt[2]'
            Info: Total cell delay = 2.980 ns ( 36.47 % )
            Info: Total interconnect delay = 5.191 ns ( 63.53 % )
    Info: + Micro clock to output delay of source is 0.202 ns
    Info: + Micro setup delay of destination is 0.011 ns
Info: tsu for register "midscnt[3]" (data pin = "sdata", clock pin = "clk") is -0.853 ns
    Info: + Longest pin to register delay is 7.307 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_R3; Fanout = 4; PIN Node = 'sdata'
        Info: 2: + IC(4.973 ns) + CELL(0.518 ns) = 6.490 ns; Loc. = LC_X2_Y22_N6; Fanout = 2; COMB Node = 'midscnt[0]~131COUT1_148'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 6.561 ns; Loc. = LC_X2_Y22_N7; Fanout = 2; COMB Node = 'midscnt[1]~135COUT1'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 6.632 ns; Loc. = LC_X2_Y22_N8; Fanout = 1; COMB Node = 'midscnt[2]~139COUT1_149'
        Info: 5: + IC(0.000 ns) + CELL(0.675 ns) = 7.307 ns; Loc. = LC_X2_Y22_N9; Fanout = 2; REG Node = 'midscnt[3]'
        Info: Total cell delay = 2.334 ns ( 31.94 % )
        Info: Total interconnect delay = 4.973 ns ( 68.06 % )
    Info: + Micro setup delay of destination is 0.011 ns
    Info: - Shortest clock path from clock "clk" to destination register is 8.171 ns
        Info: 1: + IC(0.000 ns) + CELL(1.490 ns) = 1.490 ns; Loc. = PIN_N8; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(1.454 ns) + CELL(0.846 ns) = 3.790 ns; Loc. = LC_X1_Y25_N2; Fanout = 32; REG Node = 'mmid'
        Info: 3: + IC(3.737 ns) + CELL(0.644 ns) = 8.171 ns; Loc. = LC_X2_Y22_N9; Fanout = 2; REG Node = 'midscnt[3]'
        Info: Total cell delay = 2.980 ns ( 36.47 % )
        Info: Total interconnect delay = 5.191 ns ( 63.53 % )
Info: tco from clock "clk" to destination pin "pdata[4]" through register "pdata[4]~reg0" is 12.982 ns
    Info: + Longest clock path from clock "clk" to source register is 8.171 ns
        Info: 1: + IC(0.000 ns) + CELL(1.490 ns) = 1.490 ns; Loc. = PIN_N8; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(1.454 ns) + CELL(0.846 ns) = 3.790 ns; Loc. = LC_X1_Y25_N2; Fanout = 32; REG Node = 'mmid'
        Info: 3: + IC(3.737 ns) + CELL(0.644 ns) = 8.171 ns; Loc. = LC_X5_Y22_N8; Fanout = 1; REG Node = 'pdata[4]~reg0'
        Info: Total cell delay = 2.980 ns ( 36.47 % )
        Info: Total interconnect delay = 5.191 ns ( 63.53 % )
    Info: + Micro clock to output delay of source is 0.202 ns
    Info: + Longest register to pin delay is 4.609 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y22_N8; Fanout = 1; REG Node = 'pdata[4]~reg0'
        Info: 2: + IC(2.114 ns) + CELL(2.495 ns) = 4.609 ns; Loc. = PIN_R6; Fanout = 0; PIN Node = 'pdata[4]'
        Info: Total cell delay = 2.495 ns ( 54.13 % )
        Info: Total interconnect delay = 2.114 ns ( 45.87 % )
Info: th for register "midscnt[0]" (data pin = "sdata", clock pin = "clk") is 1.643 ns
    Info: + Longest clock path from clock "clk" to destination register is 8.171 ns
        Info: 1: + IC(0.000 ns) + CELL(1.490 ns) = 1.490 ns; Loc. = PIN_N8; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(1.454 ns) + CELL(0.846 ns) = 3.790 ns; Loc. = LC_X1_Y25_N2; Fanout = 32; REG Node = 'mmid'
        Info: 3: + IC(3.737 ns) + CELL(0.644 ns) = 8.171 ns; Loc. = LC_X2_Y22_N6; Fanout = 4; REG Node = 'midscnt[0]'
        Info: Total cell delay = 2.980 ns ( 36.47 % )
        Info: Total interconnect delay = 5.191 ns ( 63.53 % )
    Info: + Micro hold delay of destination is 0.114 ns
    Info: - Shortest pin to register delay is 6.642 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_R3; Fanout = 4; PIN Node = 'sdata'
        Info: 2: + IC(4.973 ns) + CELL(0.670 ns) = 6.642 ns; Loc. = LC_X2_Y22_N6; Fanout = 4; REG Node = 'midscnt[0]'
        Info: Total cell delay = 1.669 ns ( 25.13 % )
        Info: Total interconnect delay = 4.973 ns ( 74.87 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Mon Jan 16 15:17:56 2006
    Info: Elapsed time: 00:00:01