receiver.map.rpt

串行输入信号经内部处理后

; Ignore translate_off and translate_on Synthesis Directives         ; Off          ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                 ; On           ; On            ;
+--------------------------------------------------------------------+--------------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                       ;
+----------------------------------+-----------------+-----------------+---------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path          ;
+----------------------------------+-----------------+-----------------+---------------------------------------+
; receiver.vhd                     ; yes             ; User VHDL File  ; C:/altera/experi/experi2/receiver.vhd ;
+----------------------------------+-----------------+-----------------+---------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 43      ;
; Total combinational functions     ; 26      ;
;     -- Total 4-input functions    ; 9       ;
;     -- Total 3-input functions    ; 4       ;
;     -- Total 2-input functions    ; 5       ;
;     -- Total 1-input functions    ; 6       ;
;     -- Total 0-input functions    ; 2       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 32      ;
; Total logic cells in carry chains ; 8       ;
; I/O pins                          ; 11      ;
; Maximum fan-out node              ; mmid    ;
; Maximum fan-out                   ; 32      ;
; Total fan-out                     ; 185     ;
; Average fan-out                   ; 3.43    ;
+-----------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                        ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |receiver                  ; 43 (43)     ; 32           ; 0           ; 0            ; 0       ; 0         ; 0         ; 11   ; 0            ; 11 (11)      ; 17 (17)           ; 15 (15)          ; 8 (8)           ; |receiver           ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 32    ;
; Number of registers using Synchronous Clear  ; 4     ;
; Number of registers using Synchronous Load   ; 4     ;
; Number of registers using Asynchronous Clear ; 18    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 31    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; readn~reg0                             ; 1       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |receiver|midscnt[3]       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/experi/experi2/receiver.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Jan 16 15:17:18 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off receiver -c receiver
Info: Found 2 design units, including 1 entities, in source file receiver.vhd
    Info: Found design unit 1: receiver-des
    Info: Found entity 1: receiver
Info: Elaborating entity "receiver" for the top level hierarchy
Warning: VHDL Process Statement warning at receiver.vhd(27): signal "mmid" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at receiver.vhd(33): signal "midstate" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Registers with preset signals will power-up high
Info: Implemented 54 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 9 output pins
    Info: Implemented 43 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Mon Jan 16 15:17:20 2006
    Info: Elapsed time: 00:00:03