fifo.tan.qmsg

8*8位的先入先出（fifo）数据缓冲器的vhdl源程序

{ "Info" "ITDB_TSU_RESULT" "ram~71 wr clk 7.358 ns register " "Info: tsu for register \"ram~71\" (data pin = \"wr\", clock pin = \"clk\") is 7.358 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.008 ns + Longest pin register " "Info: + Longest pin to register delay is 11.008 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.312 ns) 1.312 ns wr 1 PIN PIN_F12 6 " "Info: 1: + IC(0.000 ns) + CELL(1.312 ns) = 1.312 ns; Loc. = PIN_F12; Fanout = 6; PIN Node = 'wr'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "" { wr } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.032 ns) + CELL(0.244 ns) 6.588 ns process0~0 2 COMB LC_X34_Y42_N5 5 " "Info: 2: + IC(5.032 ns) + CELL(0.244 ns) = 6.588 ns; Loc. = LC_X34_Y42_N5; Fanout = 5; COMB Node = 'process0~0'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "5.276 ns" { wr process0~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.092 ns) + CELL(0.244 ns) 8.924 ns rtl~4 3 COMB LC_X36_Y42_N8 8 " "Info: 3: + IC(2.092 ns) + CELL(0.244 ns) = 8.924 ns; Loc. = LC_X36_Y42_N8; Fanout = 8; COMB Node = 'rtl~4'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "2.336 ns" { process0~0 rtl~4 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.250 ns) + CELL(0.834 ns) 11.008 ns ram~71 4 REG LC_X35_Y44_N9 1 " "Info: 4: + IC(1.250 ns) + CELL(0.834 ns) = 11.008 ns; Loc. = LC_X35_Y44_N9; Fanout = 1; REG Node = 'ram~71'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "2.084 ns" { rtl~4 ram~71 } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.634 ns 23.93 % " "Info: Total cell delay = 2.634 ns ( 23.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.374 ns 76.07 % " "Info: Total interconnect delay = 8.374 ns ( 76.07 % )" {  } {  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "11.008 ns" { wr process0~0 rtl~4 ram~71 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.008 ns" { wr wr~out0 process0~0 rtl~4 ram~71 } { 0.000ns 0.000ns 5.032ns 2.092ns 1.250ns } { 0.000ns 1.312ns 0.244ns 0.244ns 0.834ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.011 ns + " "Info: + Micro setup delay of destination is 0.011 ns" {  } { { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.661 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.661 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns clk 1 CLK PIN_M24 84 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 84; CLK Node = 'clk'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "" { clk } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.142 ns) + CELL(0.644 ns) 3.661 ns ram~71 2 REG LC_X35_Y44_N9 1 " "Info: 2: + IC(2.142 ns) + CELL(0.644 ns) = 3.661 ns; Loc. = LC_X35_Y44_N9; Fanout = 1; REG Node = 'ram~71'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "2.786 ns" { clk ram~71 } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.519 ns 41.49 % " "Info: Total cell delay = 1.519 ns ( 41.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.142 ns 58.51 % " "Info: Total interconnect delay = 2.142 ns ( 58.51 % )" {  } {  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "3.661 ns" { clk ram~71 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.661 ns" { clk clk~out0 ram~71 } { 0.000ns 0.000ns 2.142ns } { 0.000ns 0.875ns 0.644ns } } }  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "11.008 ns" { wr process0~0 rtl~4 ram~71 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.008 ns" { wr wr~out0 process0~0 rtl~4 ram~71 } { 0.000ns 0.000ns 5.032ns 2.092ns 1.250ns } { 0.000ns 1.312ns 0.244ns 0.244ns 0.834ns } } } { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "3.661 ns" { clk ram~71 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.661 ns" { clk clk~out0 ram~71 } { 0.000ns 0.000ns 2.142ns } { 0.000ns 0.875ns 0.644ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[1\] rp\[1\] 16.482 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[1\]\" through register \"rp\[1\]\" is 16.482 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.661 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.661 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns clk 1 CLK PIN_M24 84 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 84; CLK Node = 'clk'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "" { clk } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.142 ns) + CELL(0.644 ns) 3.661 ns rp\[1\] 2 REG LC_X35_Y44_N0 30 " "Info: 2: + IC(2.142 ns) + CELL(0.644 ns) = 3.661 ns; Loc. = LC_X35_Y44_N0; Fanout = 30; REG Node = 'rp\[1\]'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "2.786 ns" { clk rp[1] } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.519 ns 41.49 % " "Info: Total cell delay = 1.519 ns ( 41.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.142 ns 58.51 % " "Info: Total interconnect delay = 2.142 ns ( 58.51 % )" {  } {  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "3.661 ns" { clk rp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.661 ns" { clk clk~out0 rp[1] } { 0.000ns 0.000ns 2.142ns } { 0.000ns 0.875ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.202 ns + " "Info: + Micro clock to output delay of source is 0.202 ns" {  } { { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.619 ns + Longest register pin " "Info: + Longest register to pin delay is 12.619 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rp\[1\] 1 REG LC_X35_Y44_N0 30 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y44_N0; Fanout = 30; REG Node = 'rp\[1\]'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "" { rp[1] } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.602 ns) + CELL(0.381 ns) 1.983 ns ram~188 2 COMB LC_X36_Y42_N7 1 " "Info: 2: + IC(1.602 ns) + CELL(0.381 ns) = 1.983 ns; Loc. = LC_X36_Y42_N7; Fanout = 1; COMB Node = 'ram~188'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "1.983 ns" { rp[1] ram~188 } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.411 ns) + CELL(0.527 ns) 2.921 ns ram~189 3 COMB LC_X36_Y42_N4 1 " "Info: 3: + IC(0.411 ns) + CELL(0.527 ns) = 2.921 ns; Loc. = LC_X36_Y42_N4; Fanout = 1; COMB Node = 'ram~189'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "0.938 ns" { ram~188 ram~189 } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.521 ns) + CELL(0.527 ns) 4.969 ns dout~1462 4 COMB LC_X34_Y44_N2 1 " "Info: 4: + IC(1.521 ns) + CELL(0.527 ns) = 4.969 ns; Loc. = LC_X34_Y44_N2; Fanout = 1; COMB Node = 'dout~1462'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "2.048 ns" { ram~189 dout~1462 } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.647 ns) + CELL(0.381 ns) 5.997 ns dout~1463 5 COMB LC_X35_Y44_N3 2 " "Info: 5: + IC(0.647 ns) + CELL(0.381 ns) = 5.997 ns; Loc. = LC_X35_Y44_N3; Fanout = 2; COMB Node = 'dout~1463'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "1.028 ns" { dout~1462 dout~1463 } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.344 ns) 8.341 ns dout\[1\]\$latch 6 COMB LOOP LC_X25_Y45_N2 2 " "Info: 6: + IC(0.000 ns) + CELL(2.344 ns) = 8.341 ns; Loc. = LC_X25_Y45_N2; Fanout = 2; COMB LOOP Node = 'dout\[1\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "dout\[1\]\$latch LC_X25_Y45_N2 " "Info: Loc. = LC_X25_Y45_N2; Node \"dout\[1\]\$latch\"" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "" { dout[1]$latch } "NODE_NAME" } "" } }  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "" { dout[1]$latch } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 82 -1 0 } } { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "2.344 ns" { dout~1463 dout[1]$latch } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 82 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.774 ns) + CELL(2.504 ns) 12.619 ns dout\[1\] 7 PIN PIN_A10 0 " "Info: 7: + IC(1.774 ns) + CELL(2.504 ns) = 12.619 ns; Loc. = PIN_A10; Fanout = 0; PIN Node = 'dout\[1\]'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "4.278 ns" { dout[1]$latch dout[1] } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.664 ns 52.81 % " "Info: Total cell delay = 6.664 ns ( 52.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.955 ns 47.19 % " "Info: Total interconnect delay = 5.955 ns ( 47.19 % )" {  } {  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "12.619 ns" { rp[1] ram~188 ram~189 dout~1462 dout~1463 dout[1]$latch dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.619 ns" { rp[1] ram~188 ram~189 dout~1462 dout~1463 dout[1]$latch dout[1] } { 0.000ns 1.602ns 0.411ns 1.521ns 0.647ns 0.000ns 1.774ns } { 0.000ns 0.381ns 0.527ns 0.527ns 0.381ns 2.344ns 2.504ns } } }  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "3.661 ns" { clk rp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.661 ns" { clk clk~out0 rp[1] } { 0.000ns 0.000ns 2.142ns } { 0.000ns 0.875ns 0.644ns } } } { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "12.619 ns" { rp[1] ram~188 ram~189 dout~1462 dout~1463 dout[1]$latch dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.619 ns" { rp[1] ram~188 ram~189 dout~1462 dout~1463 dout[1]$latch dout[1] } { 0.000ns 1.602ns 0.411ns 1.521ns 0.647ns 0.000ns 1.774ns } { 0.000ns 0.381ns 0.527ns 0.527ns 0.381ns 2.344ns 2.504ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "rd dout\[4\] 8.771 ns Longest " "Info: Longest tpd from source pin \"rd\" to destination pin \"dout\[4\]\" is 8.771 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns rd 1 PIN PIN_M26 21 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_M26; Fanout = 21; PIN Node = 'rd'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "" { rd } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.895 ns) 3.894 ns dout\[4\]\$latch 2 COMB LOOP LC_X34_Y44_N7 2 " "Info: 2: + IC(0.000 ns) + CELL(2.895 ns) = 3.894 ns; Loc. = LC_X34_Y44_N7; Fanout = 2; COMB LOOP Node = 'dout\[4\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "dout\[4\]\$latch LC_X34_Y44_N7 " "Info: Loc. = LC_X34_Y44_N7; Node \"dout\[4\]\$latch\"" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "" { dout[4]$latch } "NODE_NAME" } "" } }  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "" { dout[4]$latch } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 82 -1 0 } } { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "2.895 ns" { rd dout[4]$latch } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 82 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.373 ns) + CELL(2.504 ns) 8.771 ns dout\[4\] 3 PIN PIN_G10 0 " "Info: 3: + IC(2.373 ns) + CELL(2.504 ns) = 8.771 ns; Loc. = PIN_G10; Fanout = 0; PIN Node = 'dout\[4\]'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "4.877 ns" { dout[4]$latch dout[4] } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.398 ns 72.94 % " "Info: Total cell delay = 6.398 ns ( 72.94 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.373 ns 27.06 % " "Info: Total interconnect delay = 2.373 ns ( 27.06 % )" {  } {  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "8.771 ns" { rd dout[4]$latch dout[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.771 ns" { rd rd~out0 dout[4]$latch dout[4] } { 0.000ns 0.000ns 0.000ns 2.373ns } { 0.000ns 0.999ns 2.895ns 2.504ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "in_full rd clk -0.674 ns register " "Info: th for register \"in_full\" (data pin = \"rd\", clock pin = \"clk\") is -0.674 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.654 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns clk 1 CLK PIN_M24 84 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 84; CLK Node = 'clk'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "" { clk } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.135 ns) + CELL(0.644 ns) 3.654 ns in_full 2 REG LC_X34_Y42_N9 6 " "Info: 2: + IC(2.135 ns) + CELL(0.644 ns) = 3.654 ns; Loc. = LC_X34_Y42_N9; Fanout = 6; REG Node = 'in_full'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "2.779 ns" { clk in_full } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.519 ns 41.57 % " "Info: Total cell delay = 1.519 ns ( 41.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.135 ns 58.43 % " "Info: Total interconnect delay = 2.135 ns ( 58.43 % )" {  } {  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "3.654 ns" { clk in_full } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.654 ns" { clk clk~out0 in_full } { 0.000ns 0.000ns 2.135ns } { 0.000ns 0.875ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.114 ns + " "Info: + Micro hold delay of destination is 0.114 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.442 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.442 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns rd 1 PIN PIN_M26 21 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_M26; Fanout = 21; PIN Node = 'rd'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "" { rd } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.773 ns) + CELL(0.670 ns) 4.442 ns in_full 2 REG LC_X34_Y42_N9 6 " "Info: 2: + IC(2.773 ns) + CELL(0.670 ns) = 4.442 ns; Loc. = LC_X34_Y42_N9; Fanout = 6; REG Node = 'in_full'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "3.443 ns" { rd in_full } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.669 ns 37.57 % " "Info: Total cell delay = 1.669 ns ( 37.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.773 ns 62.43 % " "Info: Total interconnect delay = 2.773 ns ( 62.43 % )" {  } {  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "4.442 ns" { rd in_full } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.442 ns" { rd rd~out0 in_full } { 0.000ns 0.000ns 2.773ns } { 0.000ns 0.999ns 0.670ns } } }  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "3.654 ns" { clk in_full } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.654 ns" { clk clk~out0 in_full } { 0.000ns 0.000ns 2.135ns } { 0.000ns 0.875ns 0.644ns } } } { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "4.442 ns" { rd in_full } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.442 ns" { rd rd~out0 in_full } { 0.000ns 0.000ns 2.773ns } { 0.000ns 0.999ns 0.670ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 10 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 15 21:53:28 2006 " "Info: Processing ended: Sun Jan 15 21:53:28 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}