fifo.tan.qmsg

8*8位的先入先出（fifo）数据缓冲器的vhdl源程序

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dout\[4\]\$latch " "Info: Node \"dout\[4\]\$latch\"" {  } { { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 82 -1 0 } }  } 0}  } { { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 82 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dout\[3\]\$latch " "Info: Node \"dout\[3\]\$latch\"" {  } { { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 82 -1 0 } }  } 0}  } { { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 82 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dout\[2\]\$latch " "Info: Node \"dout\[2\]\$latch\"" {  } { { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 82 -1 0 } }  } 0}  } { { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 82 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dout\[1\]\$latch " "Info: Node \"dout\[1\]\$latch\"" {  } { { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 82 -1 0 } }  } 0}  } { { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 82 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dout\[0\]\$latch " "Info: Node \"dout\[0\]\$latch\"" {  } { { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 82 -1 0 } }  } 0}  } { { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 82 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register in_full register ram~71 190.73 MHz 5.243 ns Internal " "Info: Clock \"clk\" has Internal fmax of 190.73 MHz between source register \"in_full\" and destination register \"ram~71\" (period= 5.243 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.037 ns + Longest register register " "Info: + Longest register to register delay is 5.037 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns in_full 1 REG LC_X34_Y42_N9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y42_N9; Fanout = 6; REG Node = 'in_full'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "" { in_full } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.517 ns) + CELL(0.100 ns) 0.617 ns process0~0 2 COMB LC_X34_Y42_N5 5 " "Info: 2: + IC(0.517 ns) + CELL(0.100 ns) = 0.617 ns; Loc. = LC_X34_Y42_N5; Fanout = 5; COMB Node = 'process0~0'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "0.617 ns" { in_full process0~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.092 ns) + CELL(0.244 ns) 2.953 ns rtl~4 3 COMB LC_X36_Y42_N8 8 " "Info: 3: + IC(2.092 ns) + CELL(0.244 ns) = 2.953 ns; Loc. = LC_X36_Y42_N8; Fanout = 8; COMB Node = 'rtl~4'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "2.336 ns" { process0~0 rtl~4 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.250 ns) + CELL(0.834 ns) 5.037 ns ram~71 4 REG LC_X35_Y44_N9 1 " "Info: 4: + IC(1.250 ns) + CELL(0.834 ns) = 5.037 ns; Loc. = LC_X35_Y44_N9; Fanout = 1; REG Node = 'ram~71'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "2.084 ns" { rtl~4 ram~71 } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.178 ns 23.39 % " "Info: Total cell delay = 1.178 ns ( 23.39 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.859 ns 76.61 % " "Info: Total interconnect delay = 3.859 ns ( 76.61 % )" {  } {  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "5.037 ns" { in_full process0~0 rtl~4 ram~71 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.037 ns" { in_full process0~0 rtl~4 ram~71 } { 0.000ns 0.517ns 2.092ns 1.250ns } { 0.000ns 0.100ns 0.244ns 0.834ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.007 ns - Smallest " "Info: - Smallest clock skew is 0.007 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.661 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.661 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns clk 1 CLK PIN_M24 84 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 84; CLK Node = 'clk'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "" { clk } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.142 ns) + CELL(0.644 ns) 3.661 ns ram~71 2 REG LC_X35_Y44_N9 1 " "Info: 2: + IC(2.142 ns) + CELL(0.644 ns) = 3.661 ns; Loc. = LC_X35_Y44_N9; Fanout = 1; REG Node = 'ram~71'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "2.786 ns" { clk ram~71 } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.519 ns 41.49 % " "Info: Total cell delay = 1.519 ns ( 41.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.142 ns 58.51 % " "Info: Total interconnect delay = 2.142 ns ( 58.51 % )" {  } {  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "3.661 ns" { clk ram~71 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.661 ns" { clk clk~out0 ram~71 } { 0.000ns 0.000ns 2.142ns } { 0.000ns 0.875ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.654 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns clk 1 CLK PIN_M24 84 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 84; CLK Node = 'clk'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "" { clk } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.135 ns) + CELL(0.644 ns) 3.654 ns in_full 2 REG LC_X34_Y42_N9 6 " "Info: 2: + IC(2.135 ns) + CELL(0.644 ns) = 3.654 ns; Loc. = LC_X34_Y42_N9; Fanout = 6; REG Node = 'in_full'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "2.779 ns" { clk in_full } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.519 ns 41.57 % " "Info: Total cell delay = 1.519 ns ( 41.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.135 ns 58.43 % " "Info: Total interconnect delay = 2.135 ns ( 58.43 % )" {  } {  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "3.654 ns" { clk in_full } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.654 ns" { clk clk~out0 in_full } { 0.000ns 0.000ns 2.135ns } { 0.000ns 0.875ns 0.644ns } } }  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "3.661 ns" { clk ram~71 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.661 ns" { clk clk~out0 ram~71 } { 0.000ns 0.000ns 2.142ns } { 0.000ns 0.875ns 0.644ns } } } { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "3.654 ns" { clk in_full } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.654 ns" { clk clk~out0 in_full } { 0.000ns 0.000ns 2.135ns } { 0.000ns 0.875ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.202 ns + " "Info: + Micro clock to output delay of source is 0.202 ns" {  } {  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.011 ns + " "Info: + Micro setup delay of destination is 0.011 ns" {  } { { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 13 -1 0 } }  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "5.037 ns" { in_full process0~0 rtl~4 ram~71 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.037 ns" { in_full process0~0 rtl~4 ram~71 } { 0.000ns 0.517ns 2.092ns 1.250ns } { 0.000ns 0.100ns 0.244ns 0.834ns } } } { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "3.661 ns" { clk ram~71 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.661 ns" { clk clk~out0 ram~71 } { 0.000ns 0.000ns 2.142ns } { 0.000ns 0.875ns 0.644ns } } } { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "3.654 ns" { clk in_full } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.654 ns" { clk clk~out0 in_full } { 0.000ns 0.000ns 2.135ns } { 0.000ns 0.875ns 0.644ns } } }  } 0}