fifo.fit.qmsg

8*8位的先入先出（fifo）数据缓冲器的vhdl源程序

{ "Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "19 unused 3.30 9 10 0 " "Info: Number of I/O pins in group: 19 (unused VREF, 3.30 VCCIO, 9 input, 10 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 61 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  61 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 59 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  59 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 54 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  54 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 1 55 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  55 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 2 57 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  57 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 1 60 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  60 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 57 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  57 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 54 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  54 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use unused 0 6 " "Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use unused 0 0 " "Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use unused 0 6 " "Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "12 does not use unused 0 0 " "Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.144 ns register register " "Info: Estimated most critical path is register to register delay of 4.144 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wp\[1\] 1 REG LAB_X35_Y40 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X35_Y40; Fanout = 11; REG Node = 'wp\[1\]'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "" { wp[1] } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.125 ns) + CELL(0.381 ns) 1.506 ns rtl~119 2 COMB LAB_X34_Y42 3 " "Info: 2: + IC(1.125 ns) + CELL(0.381 ns) = 1.506 ns; Loc. = LAB_X34_Y42; Fanout = 3; COMB Node = 'rtl~119'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "1.506 ns" { wp[1] rtl~119 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.064 ns) + CELL(0.527 ns) 2.097 ns rtl~3 3 COMB LAB_X34_Y42 8 " "Info: 3: + IC(0.064 ns) + CELL(0.527 ns) = 2.097 ns; Loc. = LAB_X34_Y42; Fanout = 8; COMB Node = 'rtl~3'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "0.591 ns" { rtl~119 rtl~3 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.213 ns) + CELL(0.834 ns) 4.144 ns ram~40 4 REG LAB_X34_Y43 1 " "Info: 4: + IC(1.213 ns) + CELL(0.834 ns) = 4.144 ns; Loc. = LAB_X34_Y43; Fanout = 1; REG Node = 'ram~40'" {  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "2.047 ns" { rtl~3 ram~40 } "NODE_NAME" } "" } } { "fifo.vhd" "" { Text "C:/altera/experi/fifo.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.742 ns 42.04 % " "Info: Total cell delay = 1.742 ns ( 42.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.402 ns 57.96 % " "Info: Total interconnect delay = 2.402 ns ( 57.96 % )" {  } {  } 0}  } { { "C:/altera/experi/db/fifo_cmp.qrpt" "" { Report "C:/altera/experi/db/fifo_cmp.qrpt" Compiler "fifo" "UNKNOWN" "V1" "C:/altera/experi/db/fifo.quartus_db" { Floorplan "C:/altera/experi/" "" "4.144 ns" { wp[1] rtl~119 rtl~3 ram~40 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 15 21:53:16 2006 " "Info: Processing ended: Sun Jan 15 21:53:16 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:22 " "Info: Elapsed time: 00:00:22" {  } {  } 0}  } {  } 0}