fifo.map.rpt

8*8位的先入先出（fifo）数据缓冲器的vhdl源程序

; Total combinational functions   ; 78        ;
;     -- Total 4-input functions  ; 60        ;
;     -- Total 3-input functions  ; 14        ;
;     -- Total 2-input functions  ; 4         ;
;     -- Total 1-input functions  ; 0         ;
;     -- Total 0-input functions  ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 84        ;
; I/O pins                        ; 22        ;
; Maximum fan-out node            ; clk       ;
; Maximum fan-out                 ; 84        ;
; Total fan-out                   ; 544       ;
; Average fan-out                 ; 2.99      ;
+---------------------------------+-----------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                        ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |fifo                      ; 160 (160)   ; 84           ; 0           ; 0            ; 0       ; 0         ; 0         ; 22   ; 0            ; 76 (76)      ; 82 (82)           ; 2 (2)            ; 0 (0)           ; |fifo               ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------+
; Registers Protected by SYN_PRESERVE, DONT_TOUCH                                        ;
+---------------+---------------------------+--------------------------------------------+
; Register Name ; Protected by SYN_PRESERVE ; Not to be Touched by Netlist Optimizations ;
+---------------+---------------------------+--------------------------------------------+
; ram_28        ; yes                       ; yes                                        ;
; rp[1]         ; yes                       ; yes                                        ;
; rp[0]         ; yes                       ; yes                                        ;
; rp[2]         ; yes                       ; yes                                        ;
; ram_32        ; yes                       ; yes                                        ;
; ram_31        ; yes                       ; yes                                        ;
; ram_30        ; yes                       ; yes                                        ;
; ram_29        ; yes                       ; yes                                        ;
; ram_27        ; yes                       ; yes                                        ;
; ram_26        ; yes                       ; yes                                        ;
; ram_25        ; yes                       ; yes                                        ;
; ram_24        ; yes                       ; yes                                        ;
; ram_23        ; yes                       ; yes                                        ;
; ram_22        ; yes                       ; yes                                        ;
; ram_21        ; yes                       ; yes                                        ;
+---------------+---------------------------+--------------------------------------------+


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; dout[0]$latch                                 ;   ;
; dout[1]$latch                                 ;   ;
; dout[2]$latch                                 ;   ;
; dout[3]$latch                                 ;   ;
; dout[4]$latch                                 ;   ;
; dout[5]$latch                                 ;   ;
; dout[6]$latch                                 ;   ;
; dout[7]$latch                                 ;   ;
; Number of user-specified and inferred latches ; 8 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 84    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 8     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 70    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; in_empty                               ; 5       ;
; rp[0]                                  ; 29      ;
; rp[2]                                  ; 20      ;
; rp[1]                                  ; 30      ;
; Total number of inverted registers = 4 ;         ;
+----------------------------------------+---------+


+----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |fifo ;
+----------------+-------+---------------------------------------------+
; Parameter Name ; Value ; Type                                        ;
+----------------+-------+---------------------------------------------+
; w              ; 8     ; Integer                                     ;
; k              ; 8     ; Integer                                     ;
+----------------+-------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/experi/fifo.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sun Jan 15 21:52:49 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fifo -c fifo
Info: Found 2 design units, including 1 entities, in source file fifo.vhd
    Info: Found design unit 1: fifo-fifo_arch
    Info: Found entity 1: fifo
Info: Elaborating entity "fifo" for the top level hierarchy
Info: Registers with preset signals will power-up high
Info: Implemented 182 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 10 output pins
    Info: Implemented 160 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Sun Jan 15 21:52:53 2006
    Info: Elapsed time: 00:00:04