fifo.fit.summary

8*8位的先入先出（fifo）数据缓冲器的vhdl源程序

Flow Status : Successful - Sun Jan 15 21:53:16 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : fifo
Top-level Entity Name : fifo
Family : Stratix
Device : EP1S25F672C7
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 117 / 25,660 ( < 1 % )
Total pins : 22 / 474 ( 4 % )
Total virtual pins : 0
Total memory bits : 0 / 1,944,576 ( 0 % )
DSP block 9-bit elements : 0 / 80 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )