📄 mcode.tan.rpt
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Timing Analyzer report for mcode
Thu Dec 15 10:07:53 2005
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+------+------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 7.445 ns ; m[0] ; code ; clk ; ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; m[2] ; m[2] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S25F672C7 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; m[2] ; m[2] ; clk ; clk ; None ; None ; 1.183 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; m[1] ; m[2] ; clk ; clk ; None ; None ; 0.942 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; m[2] ; m[1] ; clk ; clk ; None ; None ; 0.772 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; m[0] ; m[2] ; clk ; clk ; None ; None ; 0.763 ns ;
; N/A ; Restricted to 390.02 MHz ( period = 2.564 ns ) ; m[1] ; m[0] ; clk ; clk ; None ; None ; 0.625 ns ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------+------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------+------+------------+
; N/A ; None ; 7.445 ns ; m[0] ; code ; clk ;
+-------+--------------+------------+------+------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Thu Dec 15 10:07:52 2005
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mcode -c mcode --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 390.02 MHz between source register "m[2]" and destination register "m[2]"
Info: fmax restricted to clock pin edge rate 2.564 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 1.183 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y45_N2; Fanout = 2; REG Node = 'm[2]'
Info: 2: + IC(0.513 ns) + CELL(0.670 ns) = 1.183 ns; Loc. = LC_X1_Y45_N2; Fanout = 2; REG Node = 'm[2]'
Info: Total cell delay = 0.670 ns ( 56.64 % )
Info: Total interconnect delay = 0.513 ns ( 43.36 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 3.717 ns
Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 3; CLK Node = 'clk'
Info: 2: + IC(2.198 ns) + CELL(0.644 ns) = 3.717 ns; Loc. = LC_X1_Y45_N2; Fanout = 2; REG Node = 'm[2]'
Info: Total cell delay = 1.519 ns ( 40.87 % )
Info: Total interconnect delay = 2.198 ns ( 59.13 % )
Info: - Longest clock path from clock "clk" to source register is 3.717 ns
Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 3; CLK Node = 'clk'
Info: 2: + IC(2.198 ns) + CELL(0.644 ns) = 3.717 ns; Loc. = LC_X1_Y45_N2; Fanout = 2; REG Node = 'm[2]'
Info: Total cell delay = 1.519 ns ( 40.87 % )
Info: Total interconnect delay = 2.198 ns ( 59.13 % )
Info: + Micro clock to output delay of source is 0.202 ns
Info: + Micro setup delay of destination is 0.011 ns
Info: tco from clock "clk" to destination pin "code" through register "m[0]" is 7.445 ns
Info: + Longest clock path from clock "clk" to source register is 3.717 ns
Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 3; CLK Node = 'clk'
Info: 2: + IC(2.198 ns) + CELL(0.644 ns) = 3.717 ns; Loc. = LC_X1_Y45_N4; Fanout = 2; REG Node = 'm[0]'
Info: Total cell delay = 1.519 ns ( 40.87 % )
Info: Total interconnect delay = 2.198 ns ( 59.13 % )
Info: + Micro clock to output delay of source is 0.202 ns
Info: + Longest register to pin delay is 3.526 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y45_N4; Fanout = 2; REG Node = 'm[0]'
Info: 2: + IC(1.031 ns) + CELL(2.495 ns) = 3.526 ns; Loc. = PIN_F4; Fanout = 0; PIN Node = 'code'
Info: Total cell delay = 2.495 ns ( 70.76 % )
Info: Total interconnect delay = 1.031 ns ( 29.24 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Thu Dec 15 10:07:53 2005
Info: Elapsed time: 00:00:01
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