mcode.vhd

一个典型的m序列发生器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mcode is 
	port(
	clk: in std_logic;
	code: out std_logic
	);
end mcode;

architecture mcode_arch of mcode is 
signal m: std_logic_vector(2 downto 0);

begin
process(clk)
begin 
if clk'event and clk='1' then
	m(0)<=m(1);
	m(1)<=m(2);
end if;
end process;

process(clk)
begin 
if clk'event and clk='1' then
	m(2)<=(m(1) xor m(0)) or (not (m(0) or m(1) or m(2)));
end if;
end process;
code<=m(0);

end mcode_arch;