全加器的设计.txt

全加器的详细设计思路和用VHDL语言编写的详细源代码

library  ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity plus2 IS
PORT(x,y,cin: IN std_logic;
     S,co: out std_logic);
END ;

ARCHITECTURE aaa OF plus2 IS
signal temp: std_logic_vector(2 downto 0);
Begin
temp <=x&y&cin;
Process(temp)
begin
Case temp is
When "000"=>s<='0';
            co<='0';
When "001"|"010"|"100"=>s<='1';
                        co<='0';
When "011"|"101"|"110"=>s<='0';
                        co<='1';
When "111"=>s<='1';
            co<='1';
When others=>s<='X';
             co<='X';
End case;
End process;
end aaa;