cpu_mm_manager3.sim.rpt

利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.

Simulator report for cpu_mm_manager3
Tue May 10 21:37:56 2005
Version 4.1 Build 181 06/29/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. Simulator INI Usage
  6. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+--------------------------------------------+
; Simulator Summary                          ;
+-----------------------------+--------------+
; Type                        ; Value        ;
+-----------------------------+--------------+
; Simulation Start Time       ; 0 ps         ;
; Simulation End Time         ; 2.0 us       ;
; Simulation Netlist Size     ; 610 nodes    ;
; Simulation Coverage         ;      68.96 % ;
; Total Number of Transitions ; 32838        ;
+-----------------------------+--------------+


+-------------------------------------------------------------------------+
; Simulator Settings                                                      ;
+-------------------------------------------------------+-----------------+
; Option                                                ; Setting         ;
+-------------------------------------------------------+-----------------+
; Simulation mode                                       ; Timing          ;
; Start time                                            ; 0ns             ;
; Add pins automatically to simulation output waveforms ; On              ;
; Check outputs                                         ; Off             ;
; Report simulation coverage                            ; On              ;
; Detect setup and hold time violations                 ; Off             ;
; Detect glitches                                       ; Off             ;
; Estimate power consumption                            ; Off             ;
; USE_COMPILER_SETTINGS                                 ; cpu_mm_manager3 ;
; Automatically save/load simulation netlist            ; Off             ;
; Disable timing delays in Timing Simulation            ; Off             ;
+-------------------------------------------------------+-----------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue May 10 21:37:53 2005
Info: Command: quartus_sim --import_settings_files=on --export_settings_files=off cpu_mm_manager3 -c cpu_mm_manager3
Warning: Can't display state machine states -- register holding state machine bit statement~36 was synthesized away
Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT[7] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT[6] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT[5] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT[4] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT[3] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT[2] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT[1] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT[0] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT[7] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT[6] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT[5] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT[4] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT[3] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT[2] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT[1] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT[0] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT[7] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT[6] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT[5] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT[4] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT[3] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT[2] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT[1] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT[0] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT[7] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT[6] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT[5] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT[4] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT[3] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT[2] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT[1] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT[0] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name AddrR_out_OUT[3] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name AddrR_out_OUT[2] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name AddrR_out_OUT[1] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name AddrR_out_OUT[0] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name ReadMem_OUT in design.
Warning: Ignored node in vector source file. Can't find corresponding node name IP_out_OUT[3] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name IP_out_OUT[2] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name IP_out_OUT[1] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name IP_out_OUT[0] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT[7] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT[6] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT[5] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT[4] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT[3] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT[2] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT[1] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT[0] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT[7] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT[6] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT[5] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT[4] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT[3] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT[2] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT[1] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT[0] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT[7] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT[6] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT[5] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT[4] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT[3] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT[2] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT[1] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT[0] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R_to_ALU_OUT[1] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R_to_ALU_OUT[0] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R_in_OUT[1] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name R_in_OUT[0] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name OP_OUT[3] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name OP_OUT[2] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name OP_OUT[1] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name OP_OUT[0] in design.
Warning: Ignored node in vector source file. Can't find corresponding node name A_in_OUT in design.
Info: Simulation coverage is      68.96 %
Info: Number of transitions in simulation is 32838
Info: Quartus II Simulator was successful. 0 errors, 75 warnings
    Info: Processing ended: Tue May 10 21:37:56 2005
    Info: Elapsed time: 00:00:03