📄 cpu_mm_manager3.map.rpt
字号:
; Number of cells with registers only ; 169 ;
; Number of cells with combinational logic and registers ; 50 ;
+--------------------------------------------------------+-------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 4 ;
; Number of registers using Asynchronous Clear ; 192 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 201 ;
; Number of registers using Output Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------+
; Hierarchy ;
+-----------+
cpu_mm_manager3
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - statement ;
+------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
; Name ; statement~39 ; statement~38 ; statement~37 ; statement~36 ; statement~35 ; statement~34 ; statement~33 ; statement~32 ; statement~31 ; statement~30 ; statement~29 ; statement~28 ;
+------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
; statement.step0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; statement.step_0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; statement.step1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; statement.step2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; statement.step3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; statement.step01 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; statement.step12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; statement.step23 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; statement.step00 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; statement.step10 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; statement.step20 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; statement.step30 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |cpu_mm_manager3 ; 611 (611) ; 219 ; 0 ; 0 ; 0 ; 0 ; 0 ; 47 ; 0 ; 392 (392) ; 169 (169) ; 50 (50) ; 16 (16) ; |cpu_mm_manager3 ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.map.eqn.
+----------------------------------------+
; Analysis & Synthesis Source Files Read ;
+---------------------+------------------+
; File Name ; Used in Netlist ;
+---------------------+------------------+
; cpu_mm_manager3.vhd ; yes ;
+---------------------+------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource ; Usage ;
+-----------------------------------+---------+
; Logic cells ; 611 ;
; Total combinational functions ; 442 ;
; Total 4-input functions ; 316 ;
; Total 3-input functions ; 81 ;
; Total 2-input functions ; 45 ;
; Total 1-input functions ; 0 ;
; Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 219 ;
; Total logic cells in carry chains ; 16 ;
; I/O pins ; 47 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 219 ;
; Total fan-out ; 2432 ;
; Average fan-out ; 3.70 ;
+-----------------------------------+---------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Mon May 09 11:17:24 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off cpu_mm_manager3 -c cpu_mm_manager3
Info: Found 3 design units, including 1 entities, in source file cpu_mm_manager3.vhd
Info: Found design unit 1: my_own
Info: Found design unit 2: cpu_mm_manager3-CPU_manager_mm_arc3
Info: Found entity 1: cpu_mm_manager3
Warning: VHDL Signal Declaration warning at cpu_mm_manager3.vhd(41): ignored default value for signal op
Warning: VHDL Signal Declaration warning at cpu_mm_manager3.vhd(42): ignored default value for signal statement
Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(128): signal or variable bus_wire may not be assigned a new value in every possible path through the Process Statement. Signal or variable bus_wire holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: VHDL Case Statement information at cpu_mm_manager3.vhd(196): OTHERS choice is never selected
Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(209): signal statement is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(211): signal statement is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(174): signal or variable alu_out may not be assigned a new value in every possible path through the Process Statement. Signal or variable alu_out holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: VHDL Case Statement information at cpu_mm_manager3.vhd(951): OTHERS choice is never selected
Info: VHDL Case Statement information at cpu_mm_manager3.vhd(971): OTHERS choice is never selected
Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(1018): signal or variable dataout may not be assigned a new value in every possible path through the Process Statement. Signal or variable dataout holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(1028): signal or variable memaddr may not be assigned a new value in every possible path through the Process Statement. Signal or variable memaddr holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(1041): signal or variable cpudataout may not be assigned a new value in every possible path through the Process Statement. Signal or variable cpudataout holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(1054): signal or variable mem_data_in may not be assigned a new value in every possible path through the Process Statement. Signal or variable mem_data_in holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(1066): signal or variable addrr_in may not be assigned a new value in every possible path through the Process Statement. Signal or variable addrr_in holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Ignored 48 buffer(s)
Info: Ignored 48 SOFT buffer(s)
Info: State machine |cpu_mm_manager3|statement contains 12 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine |cpu_mm_manager3|statement
Info: Encoding result for state machine |cpu_mm_manager3|statement
Info: Completed encoding using 12 state bits
Info: Encoded state bit statement~39
Info: Encoded state bit statement~38
Info: Encoded state bit statement~37
Info: Encoded state bit statement~36
Info: Encoded state bit statement~35
Info: Encoded state bit statement~34
Info: Encoded state bit statement~33
Info: Encoded state bit statement~32
Info: Encoded state bit statement~31
Info: Encoded state bit statement~30
Info: Encoded state bit statement~29
Info: Encoded state bit statement~28
Info: State |cpu_mm_manager3|statement.step0 uses code string 000000000000
Info: State |cpu_mm_manager3|statement.step_0 uses code string 000000000011
Info: State |cpu_mm_manager3|statement.step1 uses code string 000000000101
Info: State |cpu_mm_manager3|statement.step2 uses code string 000000001001
Info: State |cpu_mm_manager3|statement.step3 uses code string 000000010001
Info: State |cpu_mm_manager3|statement.step01 uses code string 000000100001
Info: State |cpu_mm_manager3|statement.step12 uses code string 000001000001
Info: State |cpu_mm_manager3|statement.step23 uses code string 000010000001
Info: State |cpu_mm_manager3|statement.step00 uses code string 000100000001
Info: State |cpu_mm_manager3|statement.step10 uses code string 001000000001
Info: State |cpu_mm_manager3|statement.step20 uses code string 010000000001
Info: State |cpu_mm_manager3|statement.step30 uses code string 100000000001
Warning: Reduced register statement~36 with stuck data_in port to stuck value GND
Warning: Converted TRI buffer to OR gate or removed OPNDRN
Warning: Converting TRI node DataorALU_to_bus~0 that feeds logic to an OR gate
Warning: Converting TRI node IPorAddrOut~0 that feeds logic to an OR gate
Info: Registers with preset signals will power-up high
Info: Implemented 658 device resources after synthesis - the final resource count might be different
Info: Implemented 15 input pins
Info: Implemented 32 output pins
Info: Implemented 611 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings
Info: Processing ended: Mon May 09 11:17:37 2005
Info: Elapsed time: 00:00:13
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