disp.v

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

module  disp (ledout_out,ledsl_out,led_out,clr_in,clk_in,cs_in,data_in,a0_in);

input	clr_in;
input	clk_in;
input	cs_in;
input	a0_in;
input	[7:0]	data_in;

output	[7:0]	ledout_out;
output	[3:0]	ledsl_out;
output	led_out;



reg		led_reg;
reg		[23:0]	cnt_clk;

reg	[15:0]	data;
reg	[7:0]	seg_reg;
reg	[3:0]	sl_reg;
reg	[3:0]	disp_dat;
reg	[1:0]	cs_reg;
//reg			a0_reg;
reg			state;



parameter 
		Idle		=1'b0,
		Read		=1'b1;
		

assign	led_out=(clr_in)?led_reg:1'b1;
assign	ledout_out=seg_reg;
assign	ledsl_out=(clr_in&&(!cs_in))?sl_reg:4'b1111;

always @(posedge clk_in)
	begin
		if(clr_in==1'b0)
			begin
				cnt_clk<=24'b0;
			end
		else
			begin	
				cnt_clk<=cnt_clk+24'b1;
			end
	end

always@(posedge clk_in)
	begin
		if(clr_in==1'b0)
			begin
				data<=16'b0;
				state<=Idle;
				cs_reg<=2'b0;
				//a0_reg<=1'b0;
				
			end
		else
			begin
				cs_reg[1]<=cs_reg[0];
				cs_reg[0]<=cs_in;
				//a0_reg<=a0_in;
				case(state)
					Idle:
						begin
							data[15:8]<=data[15:8];
							data[7:0]<=data[7:0];
							case(cs_in)
								1'b0:state<=Idle;
								1'b1:state<=Read;	
							default:
								state<=state;	
							endcase
						end
					Read:
						begin							
							case({cs_reg,a0_in})
							3'b010:
								begin
									//data[7:0]<=data_in[7:0];
									state<=Read;
								end
							3'b011:
								begin
									//data[15:8]<=data_in[7:0];
									state<=Read;
								end
							3'b110:
								begin
									//data[7:0]<=data_in[7:0];
									state<=Read;
								end
							3'b111:
								begin
									//data[15:8]<=data_in[7:0];
									state<=Read;
								end
							3'b101:
								begin
									data[15:8]<=data_in[7:0];
									
									state<=Idle;
								end
							3'b100:
								begin
									data[7:0]<=data_in[7:0];
									state<=Idle;
								end
							default:
								begin
									data<=data;
									state<=state;
								end
							endcase
						end
				default:
					state<=Idle; 
				endcase
			end	
	end
always@(cnt_clk[22])
begin
	if(cnt_clk[22]==1'b1)
		led_reg<=1'b1;
	else
		led_reg<=1'b0;
end				

always	@(cnt_clk[14:13] or data)
	begin
		case(cnt_clk[14:13])
			2'b00:disp_dat<=data[15:12];
			2'b01:disp_dat<=data[11:8];
			2'b10:disp_dat<=data[7:4];
			2'b11:disp_dat<=data[3:0];
		endcase

		case(cnt_clk[14:13])
			2'b00:sl_reg<=4'b1110;
			2'b01:sl_reg<=4'b1101;
			2'b10:sl_reg<=4'b1011;
			2'b11:sl_reg<=4'b0111;
		endcase
	end
always@(disp_dat)
	begin
	  case(disp_dat)	
		4'h0:seg_reg<=8'hc0;
		4'h1:seg_reg<=8'hf9;
		4'h2:seg_reg<=8'ha4;
		4'h3:seg_reg<=8'hb0;
		4'h4:seg_reg<=8'h99;
		4'h5:seg_reg<=8'h92;
		4'h6:seg_reg<=8'h82;
		4'h7:seg_reg<=8'hf8;                                                                                                                            
		4'h8:seg_reg<=8'h80;
		4'h9:seg_reg<=8'h90;
		4'ha:seg_reg<=8'h88;
		4'hb:seg_reg<=8'h83;
		4'hc:seg_reg<=8'hc6;
		4'hd:seg_reg<=8'ha1;
		4'he:seg_reg<=8'h86;
		4'hf:seg_reg<=8'h8e;
	 endcase
	end			
endmodule