leospec.his

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

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# 12/11/05 21:13:32
set_working_dir F:/Verilog_Pro/disp
set part EPF10K30ATC144
set process 1
set chip TRUE
set macro FALSE
set_working_dir F:/Verilog_Pro/qep_data_bus
_gc_read_init
set input_file_list { F:/Verilog_Pro/qep_data_bus/cnt_pulse.v F:/Verilog_Pro/qep_data_bus/data_bus.v F:/Verilog_Pro/qep_data_bus/disp.v F:/Verilog_Pro/qep_data_bus/qep4.v F:/Verilog_Pro/qep_data_bus/qep_data_bus.v }
set encoding OneHot
set optimize_for area
set report brief
set -hierarchy auto
set effort quick
set hierarchy_auto TRUE
set hierarchy_preserve FALSE
set hierarchy_flatten FALSE
set output_file cnt_pulse.edf
set novendor_constraint_file FALSE
set target flex10a
_gc_read
_gc_run_init
set chip TRUE
set macro FALSE
set output_file qep_data_bus.edf
_gc_run