selectch1.vhd

完整的双向计数器VHDL 程序 大家参考

 LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 USE IEEE.STD_LOGIC_ARITH.ALL;



ENTITY   1selectch IS
	PORT(	IOW		: IN STD_LOGIC;
			CS8254	: OUT STD_LOGIC;
			IOR		: IN	STD_LOGIC;
			ADDR 	: IN	STD_LOGIC_VECTOR(9 downto 0);
			DATA	: INOUT	STD_LOGIC_VECTOR(7 downto 0);
		RESULTIN	: IN	STD_LOGIC_VECTOR(7 downto 0);
		 selectch	: OUT	STD_LOGIC_VECTOR(2 downto 0)
		);

END ENTITY;

ARCHITECTURE a OF 1SELECTCH IS
	SIGNAL INLATCH			:STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL INTERNAL_BUS_OUT	:STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL TSIG 			:STD_LOGIC;
	--SIGNAL LACH : STD_LOGIC;
BEGIN
	PROCESS(IOR,ADDR)
		--VARIABLE N: INTEGER RANGE 0 TO 3;
 		BEGIN
			
			IF( IOR='0')THEN
				IF(ADDR="1001101101")THEN
					--IF(N=3)THEN
					--	N:=0;
					--END IF;
				--CASE N IS
				--WHEN 0 =>INTERNAL_BUS_OUT<=RESULTIN(7 DOWNTO 0);
				--WHEN 1 =>INTERNAL_BUS_OUT<=RESULTIN(15 DOWNTO 8);
				--WHEN 2 =>INTERNAL_BUS_OUT<=RESULTIN(23 DOWNTO 16);
				--WHEN 3 =>INTERNAL_BUS_OUT<="ZZZZZZZZ";
				--END CASE;				
				--N:=N+1;
					INTERNAL_BUS_OUT<=RESULTIN(7 DOWNTO 0);

				ELSE INTERNAL_BUS_OUT<="ZZZZZZZZ";
				END IF;
			ELSE INTERNAL_BUS_OUT<="ZZZZZZZZ";
			END IF;
				DATA<=INTERNAL_BUS_OUT;
			END PROCESS;
	PROCESS(IOW,ADDR)
		BEGIN
			IF(IOW='0')THEN
				IF(ADDR="1001101110" )THEN
					SELECTCH<=DATA(2 DOWNTO 0);
				ELSIF(ADDR(9 DOWNTO 2)= "10011001") THEN
						CS8254<='0';
					ELSE
						CS8254<='1'; 				
				END IF;
			END IF;

					END PROCESS;
			END A;