play.v

用Verilog HDL 语言编写的播放梁祝的程序

module play(audiof,sys_CLK);
output audiof;
input sys_CLK;

reg[23:0] counter4Hz,counter6MHz;
reg[13:0] count,origin;
reg audiof;

reg clk_6MHz,clk_4Hz;

reg[11:0] i;
reg[4:0] j;
reg[7:0] len;


always @(posedge sys_CLK)
begin
	if(counter6MHz==3)
	begin
		counter6MHz=0;
		clk_6MHz=~clk_6MHz;
	end
	else
	begin
		counter6MHz=counter6MHz+1;
	end
end

always @(posedge sys_CLK)
begin
	if(counter4Hz==6250000)
	begin
		counter4Hz=0;
		clk_4Hz=~clk_4Hz;
	end
	else
	begin
		counter4Hz=counter4Hz+1;
	end
end


always @(posedge clk_6MHz)
begin
	if(count==16383)
	begin
		count=origin;
		audiof=~audiof;
	end
	else
		count=count+1;
end

always @(posedge clk_4Hz)
begin
	case(i)
	'b000000010000:origin='d010647;  //middle
	'b000000100000:origin='d011272;
	'b000000110000:origin='d011831;
	'b000001000000:origin='d012087;
	'b000001010000:origin='d012556;
	'b000001100000:origin='d012974;
	'b000001110000:origin='d013346;
	'b000000000001:origin='d4916;  //low
	'b000000000010:origin='d6168;
	'b000000000011:origin='d7281;
	'b000000000100:origin='d7791;
	'b000000000101:origin='d8730;
	'b000000000110:origin='d9565;
	'b000000000111:origin='d10310;
	'b000100000000:origin='d13516;  //high
	'b001000000000:origin='d13829;
	'b001100000000:origin='d14108;
	'b010000000000:origin='d11535;
	'b010100000000:origin='d14470;
	'b011000000000:origin='d14678;
	'b011100000000:origin='d14864;
	

	default:origin='d011111;
	endcase
end

always @(posedge clk_4Hz)
begin
     case(j)
     'd1:i='b000000000001;  //low
	'd2:i='b000000000010;
	'd3:i='b000000000011;
	'd4:i='b000000000100;
	'd5:i='b000000000101;
	'd6:i='b000000000110;
	'd7:i='b000000000111;
	'd8:i='b000000010000;  //middle
	'd9:i='b000000100000;
	'd10:i='b000000110000;
	'd11:i='b000001000000;
	'd12:i='b000001010000;
	'd13:i='b000001100000;
	'd14:i='b000001110000;
	'd15:i='b000100000000;  //high
	'd16:i='b001000000000;
	'd17:i='b001100000000;
	'd18:i='b010000000000;
	'd19:i='b010100000000;
	'd20:i='b011000000000;
	'd21:i='b011100000000;
	endcase			 
end

always @(posedge clk_4Hz)
begin
     if(len==63)
		len=0;
	else
		len=len+1;
	case(len)
     0:j=3;
     1:j=3;
     2:j=3;
     3:j=3;
     4:j=5;
     5:j=5;
     6:j=5;
     7:j=6;
     8:j=8;
     9:j=8;
     10:j=8;
     11:j=6;
     12:j=6;
     13:j=6;
     14:j=6;
     15:j=12;
     16:j=12;
     17:j=12;
     18:j=15;
     19:j=15;
     20:j=15;
     21:j=15;
     22:j=15;
     23:j=9;
     24:j=9;
     25:j=9;
     26:j=9;
     27:j=9;
     28:j=9;
     29:j=9;
     30:j=9;
     31:j=9;
     32:j=9;
     33:j=9;
     34:j=10;
     35:j=7;
     36:j=7;
     37:j=6;
     38:j=6;
     39:j=5;
     40:j=5;
     41:j=5;
     42:j=6;
     43:j=8;
     44:j=8;
     45:j=9;
     46:j=9;
     47:j=3;
     48:j=3;
     49:j=8;
     50:j=8;
     51:j=8;
     52:j=5;
     53:j=5;
     54:j=8;
     55:j=5;
     56:j=5;
     57:j=5;
     58:j=5;
     59:j=5;
     60:j=5;
     61:j=5;
     62:j=5;
     63:j=5;
endcase
     	   	
end
endmodule