play.twr

来自「用Verilog HDL 语言编写的播放梁祝的程序」· TWR 代码 · 共 41 行

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Release 6.3i Trace G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml play play.ncd -o
play.twr play.pcf


Design file:              play.ncd
Physical constraint file: play.pcf
Device,speed:             xc2s100,-5 (PRODUCTION 1.27 2004-06-25)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock sys_CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
sys_CLK        |    8.960|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Wed Jan 11 21:18:32 2006
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Peak Memory Usage: 47 MB