step_motor_degree_forward_reverse_lcd_pack.vhd
来自「將正在順時針或逆時針旋轉的步進馬達目前角度顯示在LCM上。」· VHDL 代码 · 共 52 行
VHD
52 行
--****************************************************************
--* Declare All Component Which Is Used *
--* In STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD *
--* Filename : STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD *
--****************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK is
component BIN_ADD_4BIT
port ( CIN : in std_logic;
X : in std_logic_vector(3 downto 0);
Y : in std_logic_vector(3 downto 0);
SUM : out std_logic_vector(3 downto 0);
CARRY : out std_logic);
end component;
component BCD_ADD_1DIG
port ( CIN : in std_logic;
X : in std_logic_vector(3 downto 0);
Y : in std_logic_vector(3 downto 0);
SUM : out std_logic_vector(3 downto 0);
CARRY : out std_logic);
end component;
component COMPLEMENT
port ( ADD_SUB : in std_logic;
DATA_IN : in std_logic_vector(3 downto 0);
DATA_OUT : out std_logic_vector(3 downto 0));
end component;
component BCD_ADD_SUB_1DIG
port ( CIN : in std_logic;
ADD_SUB : in std_logic;
X : in std_logic_vector(3 downto 0);
Y : in std_logic_vector(3 downto 0);
SUM : out std_logic_vector(3 downto 0);
CARRY : out std_logic);
end component;
component BCD_ADD_SUB_4DIG is
Port ( MODE : in std_logic;
X : in std_logic_vector(15 downto 0);
Y : in std_logic_vector(15 downto 0);
SUM : out std_logic_vector(15 downto 0));
end component;
end STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK;
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