bcd_add_sub_1dig.vhd

来自「將正在順時針或逆時針旋轉的步進馬達目前角度顯示在ＬＣＭ上。」· VHDL 代码 · 共 29 行

--***************************************
--*   1 Digital BCD Adder,Substractor	*
--*    Filename : BCD_ADD_SUB_1DIG.VHD	*
--***************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.all;
 
entity BCD_ADD_SUB_1DIG is
    Port ( CIN     : in std_logic;
           ADD_SUB : in std_logic;
           X       : in std_logic_vector(3 downto 0);
           Y       : in std_logic_vector(3 downto 0);
           SUM     : out std_logic_vector(3 downto 0);
           CARRY   : out std_logic);
end BCD_ADD_SUB_1DIG;

architecture Behavioral of BCD_ADD_SUB_1DIG is
  signal Y_9SC : std_logic_vector(3 downto 0);
begin

COMP    : COMPLEMENT   port map (ADD_SUB,Y,Y_9SC);
BCD_ADD : BCD_ADD_1DIG port map (CIN,X,Y_9SC,SUM,CARRY);

end Behavioral;