bin_add_4bit.vhd

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--************************************
--*      4 Bit Binary Full Adder     *
--*    Filename : BIN_ADD_4BIT.VHD   *
--************************************

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BIN_ADD_4BIT is
    port ( CIN   : std_logic;
           X     : in STD_LOGIC_VECTOR (3 downto 0);
           Y     : in STD_LOGIC_VECTOR (3 downto 0);
           SUM   : out STD_LOGIC_VECTOR (3 downto 0);
           CARRY : out STD_LOGIC);
end BIN_ADD_4BIT;

architecture BIN_ADD_4BIT_arch of BIN_ADD_4BIT is

begin
  process (X,Y,CIN)
    variable C_OUT : std_logic;
  begin
    C_OUT := CIN; 
    for i in 0 to 3 loop
      SUM(i) <=  X(i) xor Y(i) xor C_OUT;
      C_OUT  := (X(i) and Y(i)) or (X(i) and C_OUT) or (C_OUT and Y(i));
    end loop;
    CARRY   <= C_OUT;
  end process;
 
end BIN_ADD_4BIT_arch;