📄 bcd_add_sub_4dig.vhd
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--*************************************
--* 4 Digital BCD Adder,Substractor *
--* Filename : BCD_ADD_SUB_4DIG.VHD *
--*************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.all;
entity BCD_ADD_SUB_4DIG is
Port ( MODE : in std_logic;
X : in std_logic_vector(15 downto 0);
Y : in std_logic_vector(15 downto 0);
SUM : out std_logic_vector(15 downto 0));
end BCD_ADD_SUB_4DIG;
architecture Behavioral of BCD_ADD_SUB_4DIG is
signal CT : std_logic_vector(4 downto 1);
begin
ADD_SUB1 : BCD_ADD_SUB_1DIG port map (MODE ,MODE,X(3 downto 0) ,Y(3 downto 0) ,SUM(3 downto 0) ,CT(1));
ADD_SUB2 : BCD_ADD_SUB_1DIG port map (CT(1),MODE,X(7 downto 4) ,Y(7 downto 4) ,SUM(7 downto 4) ,CT(2));
ADD_SUB3 : BCD_ADD_SUB_1DIG port map (CT(2),MODE,X(11 downto 8) ,Y(11 downto 8) ,SUM(11 downto 8) ,CT(3));
ADD_SUB4 : BCD_ADD_SUB_1DIG port map (CT(3),MODE,X(15 downto 12),Y(15 downto 12),SUM(15 downto 12),CT(4));
end Behavioral;
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