__projnav.log

將正在順時針或逆時針旋轉的步進馬達目前角度顯示在ＬＣＭ上。

Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file step_motor_degree_forward_reverse_lcd.ncd.

Total REAL time to placer completion: 2 secs 
Total CPU time to placer completion: 1 secs 


Starting Router          REAL time: 2 secs 

Phase 1: 783 unrouted;       REAL time: 2 secs 

Phase 2: 755 unrouted;       REAL time: 3 secs 

Phase 3: 221 unrouted; (~0)      REAL time: 3 secs 

Phase 4: 221 unrouted; (~0)      REAL time: 3 secs 

Phase 5: 221 unrouted; (~0)      REAL time: 3 secs 

Phase 6: 0 unrouted; (~0)      REAL time: 3 secs 

Finished Router          REAL time: 3 secs 

Total REAL time to router completion: 4 secs 
Total CPU time to router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Max Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_bufgp          |  Global  |   13   |  0.000     |  0.759      |
+----------------------------+----------+--------+------------+-------------+
|       divider<15>          |   Local  |   14   |  1.388     |  4.246      |
+----------------------------+----------+--------+------------+-------------+
|       divider<25>          |   Local  |   19   |  1.259     |  3.883      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_CLK = PERIOD TIMEGRP "CLK"  25 nS   HI | 25.000ns   | 8.713ns    | 6    
  GH 50.000000 %                            |            |            |      
--------------------------------------------------------------------------------


All constraints were met.

All signals are completely routed.

Total REAL time to par completion: 4 secs 
Total CPU time to par completion: 3 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file step_motor_degree_forward_reverse_lcd.ncd.


PAR done.

Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Loading device database for application trce.exe from file
"step_motor_degree_forward_reverse_lcd.ncd".
   "step_motor_degree_forward_reverse_lcd" is an NCD, version 2.37, device
xc2s200, package pq208, speed -5
Loading device for application trce.exe from file 'v200.nph' in environment
C:/Xilinx.

Analysis completed Tue Jun 17 11:30:54 2003
--------------------------------------------------------------------------------

Generating Report ...


Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module step_motor_degree_forward_reverse_lcd . . .
PAR command line: par -w -ol 2 -t 1 step_motor_degree_forward_reverse_lcd_map.ncd step_motor_degree_forward_reverse_lcd.ncd step_motor_degree_forward_reverse_lcd.pcf
PAR completed successfully




Started process "Generate Programming File".

Release 5.1i - Bitgen F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Loading device database for application Bitgen from file
"step_motor_degree_forward_reverse_lcd.ncd".
   "step_motor_degree_forward_reverse_lcd" is an NCD, version 2.37, device
xc2s200, package pq208, speed -5
Loading device for application Bitgen from file 'v200.nph' in environment
C:/Xilinx.
Opened constraints file step_motor_degree_forward_reverse_lcd.pcf.

Tue Jun 17 11:30:56 2003

Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "step_motor_degree_forward_reverse_lcd.bit".
Bitstream generation is complete.

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK is now defined in a different file: was C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD, now is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD
WARNING:HDLParsers:3215 - Unit work/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD is now defined in a different file: was C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD, now is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD
WARNING:HDLParsers:3215 - Unit work/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BEHAVIORAL is now defined in a different file: was C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD, now is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD
WARNING:HDLParsers:3215 - Unit work/BCD_ADD_SUB_4DIG is now defined in a different file: was C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_4DIG.VHD, now is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_4DIG.VHD
WARNING:HDLParsers:3215 - Unit work/BCD_ADD_SUB_4DIG/BEHAVIORAL is now defined in a different file: was C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_4DIG.VHD, now is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_4DIG.VHD
WARNING:HDLParsers:3215 - Unit work/BCD_ADD_SUB_1DIG is now defined in a different file: was C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_1DIG.vhd, now is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_1DIG.vhd
WARNING:HDLParsers:3215 - Unit work/BCD_ADD_SUB_1DIG/BEHAVIORAL is now defined in a different file: was C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_1DIG.vhd, now is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_1DIG.vhd
WARNING:HDLParsers:3215 - Unit work/COMPLEMENT is now defined in a different file: was C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/COMPLEMENT.vhd, now is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/COMPLEMENT.vhd
WARNING:HDLParsers:3215 - Unit work/COMPLEMENT/BEHAVIORAL is now defined in a different file: was C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/COMPLEMENT.vhd, now is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/COMPLEMENT.vhd
WARNING:HDLParsers:3215 - Unit work/BCD_ADD_1DIG is now defined in a different file: was C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD, now is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD
WARNING:HDLParsers:3215 - Unit work/BCD_ADD_1DIG/BEHAVIORAL is now defined in a different file: was C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD, now is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD
WARNING:HDLParsers:3215 - Unit work/BIN_ADD_4BIT is now defined in a different file: was C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BIN_ADD_4BIT.VHD, now is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BIN_ADD_4BIT.VHD
WARNING:HDLParsers:3215 - Unit work/BIN_ADD_4BIT/BIN_ADD_4BIT_ARCH is now defined in a different file: was C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BIN_ADD_4BIT.VHD, now is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BIN_ADD_4BIT.VHD
Compiling vhdl file E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD in Library work.
Compiling vhdl file E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BIN_ADD_4BIT.VHD in Library work.
Architecture bin_add_4bit_arch of Entity bin_add_4bit is up to date.
Compiling vhdl file E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/COMPLEMENT.vhd in Library work.
Architecture behavioral of Entity complement is up to date.
Compiling vhdl file E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD in Library work.
Architecture behavioral of Entity bcd_add_1dig is up to date.
Compiling vhdl file E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_1DIG.vhd in Library work.
Architecture behavioral of Entity bcd_add_sub_1dig is up to date.
Compiling vhdl file E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_4DIG.VHD in Library work.
Architecture behavioral of Entity bcd_add_sub_4dig is up to date.
Compiling vhdl file E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD in Library work.
Architecture behavioral of Entity step_motor_degree_forward_reverse_lcd is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <step_motor_degree_forward_reverse_lcd> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <lcm_rw> in unit <step_motor_degree_forward_reverse_lcd> never changes during circuit operation. The register is replaced by logic.
Entity <step_motor_degree_forward_reverse_lcd> analyzed. Unit <step_motor_degree_forward_reverse_lcd> generated.

Analyzing Entity <bcd_add_sub_4dig> (Architecture <behavioral>).
Entity <bcd_add_sub_4dig> analyzed. Unit <bcd_add_sub_4dig> generated.

Analyzing Entity <bcd_add_sub_1dig> (Architecture <behavioral>).
Entity <bcd_add_sub_1dig> analyzed. Unit <bcd_add_sub_1dig> generated.

Analyzing Entity <complement> (Architecture <behavioral>).
Entity <complement> analyzed. Unit <complement> generated.

Analyzing Entity <bcd_add_1dig> (Architecture <behavioral>).
WARNING:Xst:753 - E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD line 31: Unconnected output port 'carry' of component 'bin_add_4bit'.
Entity <bcd_add_1dig> analyzed. Unit <bcd_add_1dig> generated.

Analyzing Entity <bin_add_4bit> (Architecture <bin_add_4bit_arch>).
Entity <bin_add_4bit> analyzed. Unit <bin_add_4bit> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <bin_add_4bit>.
    Related source file is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BIN_ADD_4BIT.VHD.
    Found 4-bit xor3 for signal <sum>.
    Summary:
	inferred   4 Xor(s).
Unit <bin_add_4bit> synthesized.


Synthesizing Unit <bcd_add_1dig>.
    Related source file is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD.
Unit <bcd_add_1dig> synthesized.


Synthesizing Unit <complement>.
    Related source file is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/COMPLEMENT.vhd.
    Found 1-bit xor2 for signal <$n0001> created at line 25.
    Found 3 1-bit 2-to-1 multiplexers.
Unit <complement> synthesized.


Synthesizing Unit <bcd_add_sub_1dig>.
    Related source file is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_1DIG.vhd.
Unit <bcd_add_sub_1dig> synthesized.


Synthesizing Unit <bcd_add_sub_4dig>.
    Related source file is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_4DIG.VHD.
WARNING:Xst:646 - Signal <ct<8>> is assigned but never used.
WARNING:Xst:646 - Signal <ct<7>> is assigned but never used.
WARNING:Xst:646 - Signal <ct<6>> is assigned but never used.
WARNING:Xst:646 - Signal <ct<5>> is assigned but never used.
Unit <bcd_add_sub_4dig> synthesized.


Synthesizing Unit <step_motor_degree_forward_reverse_lcd>.
    Related source file is E:/NEWBOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD.
    Found 1-bit register for signal <lcm_rs>.
    Found 8-bit register for signal <lcm_data>.
    Found 6-bit comparator less for signal <$n0011> created at line 65.
    Found 6-bit adder for signal <$n0019> created at line 66.
    Found 16-bit register for signal <degree>.
    Found 25-bit up counter for signal <divider>.
    Found 6-bit register for signal <lcm_init>.
    Found 4-bit register for signal <pattern>.
    Found 5 1-bit 2-to-1 multiplexers.
WARNING:Xst:646 - Signal <carry> is assigned but never used.
    Summary:
	inferred   1 Counter(s).
	inferred  23 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <step_motor_degree_forward_reverse_lcd> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 5
  16-bit register                  : 1
  6-bit register                   : 1
  1-bit register                   : 1
  8-bit register                   : 1
  4-bit register                   : 1
# Counters                         : 1
  25-bit up counter                : 1
# Multiplexers                     : 26
  2-to-1 multiplexer               : 26
# Adders/Subtractors               : 1
  6-bit adder                      : 1
# Comparators                      : 1
  6-bit comparator less            : 1
# Xors                             : 72
  1-bit xor2                       : 8
  1-bit xor3                       : 64

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/data/librtl.xst" Consulted
WARNING:Xst:1290 - Hierarchical block <Mxor__n0001> is unconnected in block <comp>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <Mxor__n0001> is unconnected in block <comp>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <Mxor__n0001> is unconnected in block <comp>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <Mxor__n0001> is unconnected in block <comp>.
   It will be removed from the design.

Optimizing unit <step_motor_degree_forward_reverse_lcd> ...

Optimizing unit <bin_add_4bit> ...

Optimizing unit <bcd_add_sub_4dig> ...

Mapping all equations...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block step_motor_degree_forward_reverse_lcd, actual ratio is 6.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-5 

 Number of Slices:                     112  out of   2352     4%  
 Number of Slice Flip Flops:            60  out of   4704     1%  
 Number of 4 input LUTs:               207  out of   4704     4%  
 Number of bonded IOBs:                 17  out of    144    11%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
divider_15:q                       | NONE                   | 15    |
divider_25:q                       | NONE                   | 20    |