__projnav.log

將正在順時針或逆時針旋轉的步進馬達目前角度顯示在ＬＣＭ上。

Completed process "Map".

Mapping Module step_motor_degree_forward_reverse_lcd . . .
MAP command line:
map -quiet -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o step_motor_degree_forward_reverse_lcd_map.ncd step_motor_degree_forward_reverse_lcd.ngd step_motor_degree_forward_reverse_lcd.pcf
Mapping Module step_motor_degree_forward_reverse_lcd: DONE



Started process "Place & Route".

Release 5.1i - Par F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.




Constraints file: step_motor_degree_forward_reverse_lcd.pcf

Loading device database for application par from file
"step_motor_degree_forward_reverse_lcd_map.ncd".
   "step_motor_degree_forward_reverse_lcd" is an NCD, version 2.37, device
xc2s200, package pq208, speed -5
Loading device for application par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  PRELIMINARY 1.25 2002-06-19.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            17 out of 140    12%
      Number of LOCed External IOBs   17 out of 17    100%

   Number of SLICEs                  105 out of 2352    4%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:989913) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
............
......
Phase 5.8 (Checksum:9a3890) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file step_motor_degree_forward_reverse_lcd.ncd.

Total REAL time to placer completion: 0 secs 
Total CPU time to placer completion: 1 secs 


Starting Router          REAL time: 0 secs 

Phase 1: 783 unrouted;       REAL time: 0 secs 

Phase 2: 755 unrouted;       REAL time: 2 secs 

Phase 3: 221 unrouted; (~0)      REAL time: 2 secs 

Phase 4: 221 unrouted; (~0)      REAL time: 2 secs 

Phase 5: 221 unrouted; (~0)      REAL time: 2 secs 

Phase 6: 0 unrouted; (~0)      REAL time: 3 secs 

Finished Router          REAL time: 3 secs 

Total REAL time to router completion: 3 secs 
Total CPU time to router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Max Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_bufgp          |  Global  |   13   |  0.000     |  0.759      |
+----------------------------+----------+--------+------------+-------------+
|       divider<15>          |   Local  |   14   |  1.388     |  4.246      |
+----------------------------+----------+--------+------------+-------------+
|       divider<25>          |   Local  |   19   |  1.259     |  3.883      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_CLK = PERIOD TIMEGRP "CLK"  25 nS   HI | 25.000ns   | 8.713ns    | 6    
  GH 50.000000 %                            |            |            |      
--------------------------------------------------------------------------------


All constraints were met.

All signals are completely routed.

Total REAL time to par completion: 3 secs 
Total CPU time to par completion: 3 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file step_motor_degree_forward_reverse_lcd.ncd.


PAR done.

Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Loading device database for application trce.exe from file
"step_motor_degree_forward_reverse_lcd.ncd".
   "step_motor_degree_forward_reverse_lcd" is an NCD, version 2.37, device
xc2s200, package pq208, speed -5
Loading device for application trce.exe from file 'v200.nph' in environment
C:/Xilinx.

Analysis completed Wed Jun 04 23:26:38 2003
--------------------------------------------------------------------------------

Generating Report ...


Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module step_motor_degree_forward_reverse_lcd . . .
PAR command line: par -w -ol 2 -t 1 step_motor_degree_forward_reverse_lcd_map.ncd step_motor_degree_forward_reverse_lcd.ncd step_motor_degree_forward_reverse_lcd.pcf
PAR completed successfully




Started process "Generate Programming File".

Release 5.1i - Bitgen F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Loading device database for application Bitgen from file
"step_motor_degree_forward_reverse_lcd.ncd".
   "step_motor_degree_forward_reverse_lcd" is an NCD, version 2.37, device
xc2s200, package pq208, speed -5
Loading device for application Bitgen from file 'v200.nph' in environment
C:/Xilinx.
Opened constraints file step_motor_degree_forward_reverse_lcd.pcf.

Wed Jun 04 23:26:39 2003

Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "step_motor_degree_forward_reverse_lcd.bit".
Bitstream generation is complete.

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD
Scanning    STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD
Scanning    STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD
Writing STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    BCD_ADD_SUB_4DIG.VHD
Scanning    STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD
Scanning    BCD_ADD_SUB_4DIG.VHD
Writing BCD_ADD_SUB_4DIG.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    BCD_ADD_1DIG.VHD
Scanning    STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD
Scanning    BCD_ADD_1DIG.VHD
Writing BCD_ADD_1DIG.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    BCD_ADD_SUB_4DIG.VHD
Scanning    STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD
Scanning    BCD_ADD_SUB_4DIG.VHD
Writing BCD_ADD_SUB_4DIG.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    BIN_ADD_4BIT.VHD
Scanning    STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD
Scanning    BIN_ADD_4BIT.VHD
Writing BIN_ADD_4BIT.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    BCD_ADD_SUB_1DIG.vhd
Scanning    STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD
Scanning    BCD_ADD_SUB_1DIG.vhd
Writing BCD_ADD_SUB_1DIG.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD
Scanning    STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD
Scanning    STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD
Writing STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD in Library work.
Compiling vhdl file C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BIN_ADD_4BIT.VHD in Library work.
Entity <bin_add_4bit> (Architecture <bin_add_4bit_arch>) compiled.
Compiling vhdl file C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/COMPLEMENT.vhd in Library work.
Architecture behavioral of Entity complement is up to date.
Compiling vhdl file C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD in Library work.