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JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    BIN_ADD_4BIT.VHD
Scanning    BCD_ADD_SUB_PACK.VHD
Scanning    BIN_ADD_4BIT.VHD
Writing BIN_ADD_4BIT.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    COMPLEMENT.vhd
Scanning    BCD_ADD_SUB_PACK.VHD
Scanning    COMPLEMENT.vhd
Writing COMPLEMENT.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    BCD_ADD_SUB_1DIG.vhd
Scanning    BCD_ADD_SUB_PACK.VHD
Scanning    BCD_ADD_SUB_1DIG.vhd
Writing BCD_ADD_SUB_1DIG.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    BCD_ADD_SUB_4DIG.VHD
Scanning    BCD_ADD_SUB_PACK.VHD
Scanning    BCD_ADD_SUB_4DIG.VHD
Writing BCD_ADD_SUB_4DIG.jhd.

JHDPARSE complete -    0 errors,    0 warnings.







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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD in Library work.
Compiling vhdl file C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BIN_ADD_4BIT.VHD in Library work.
Entity <bin_add_4bit> (Architecture <bin_add_4bit_arch>) compiled.
Compiling vhdl file C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/COMPLEMENT.vhd in Library work.
Entity <complement> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD in Library work.
Entity <bcd_add_1dig> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_1DIG.vhd in Library work.
Entity <bcd_add_sub_1dig> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_4DIG.VHD in Library work.
Entity <bcd_add_sub_4dig> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD in Library work.
Entity <step_motor_degree_forward_reverse_lcd> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <step_motor_degree_forward_reverse_lcd> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <lcm_rw> in unit <step_motor_degree_forward_reverse_lcd> never changes during circuit operation. The register is replaced by logic.
Entity <step_motor_degree_forward_reverse_lcd> analyzed. Unit <step_motor_degree_forward_reverse_lcd> generated.

Analyzing Entity <bcd_add_sub_4dig> (Architecture <behavioral>).
Entity <bcd_add_sub_4dig> analyzed. Unit <bcd_add_sub_4dig> generated.

Analyzing Entity <bcd_add_sub_1dig> (Architecture <behavioral>).
Entity <bcd_add_sub_1dig> analyzed. Unit <bcd_add_sub_1dig> generated.

Analyzing Entity <complement> (Architecture <behavioral>).
Entity <complement> analyzed. Unit <complement> generated.

Analyzing Entity <bcd_add_1dig> (Architecture <behavioral>).
WARNING:Xst:753 - C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD line 31: Unconnected output port 'carry' of component 'bin_add_4bit'.
Entity <bcd_add_1dig> analyzed. Unit <bcd_add_1dig> generated.

Analyzing Entity <bin_add_4bit> (Architecture <bin_add_4bit_arch>).
Entity <bin_add_4bit> analyzed. Unit <bin_add_4bit> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <bin_add_4bit>.
    Related source file is C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BIN_ADD_4BIT.VHD.
    Found 4-bit xor3 for signal <sum>.
    Summary:
	inferred   4 Xor(s).
Unit <bin_add_4bit> synthesized.


Synthesizing Unit <bcd_add_1dig>.
    Related source file is C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD.
Unit <bcd_add_1dig> synthesized.


Synthesizing Unit <complement>.
    Related source file is C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/COMPLEMENT.vhd.
    Found 1-bit xor2 for signal <$n0001> created at line 25.
    Found 3 1-bit 2-to-1 multiplexers.
Unit <complement> synthesized.


Synthesizing Unit <bcd_add_sub_1dig>.
    Related source file is C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_1DIG.vhd.
Unit <bcd_add_sub_1dig> synthesized.


Synthesizing Unit <bcd_add_sub_4dig>.
    Related source file is C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_4DIG.VHD.
WARNING:Xst:646 - Signal <ct<8>> is assigned but never used.
WARNING:Xst:646 - Signal <ct<7>> is assigned but never used.
WARNING:Xst:646 - Signal <ct<6>> is assigned but never used.
WARNING:Xst:646 - Signal <ct<5>> is assigned but never used.
Unit <bcd_add_sub_4dig> synthesized.


Synthesizing Unit <step_motor_degree_forward_reverse_lcd>.
    Related source file is C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD.
    Found 1-bit register for signal <lcm_rs>.
    Found 8-bit register for signal <lcm_data>.
    Found 6-bit comparator less for signal <$n0011> created at line 65.
    Found 6-bit adder for signal <$n0019> created at line 66.
    Found 16-bit register for signal <degree>.
    Found 25-bit up counter for signal <divider>.
    Found 6-bit register for signal <lcm_init>.
    Found 4-bit register for signal <pattern>.
    Found 5 1-bit 2-to-1 multiplexers.
WARNING:Xst:646 - Signal <carry> is assigned but never used.
    Summary:
	inferred   1 Counter(s).
	inferred  23 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <step_motor_degree_forward_reverse_lcd> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 5
  16-bit register                  : 1
  6-bit register                   : 1
  1-bit register                   : 1
  8-bit register                   : 1
  4-bit register                   : 1
# Counters                         : 1
  25-bit up counter                : 1
# Multiplexers                     : 26
  2-to-1 multiplexer               : 26
# Adders/Subtractors               : 1
  6-bit adder                      : 1
# Comparators                      : 1
  6-bit comparator less            : 1
# Xors                             : 72
  1-bit xor2                       : 8
  1-bit xor3                       : 64

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/data/librtl.xst" Consulted
WARNING:Xst:1290 - Hierarchical block <Mxor__n0001> is unconnected in block <comp>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <Mxor__n0001> is unconnected in block <comp>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <Mxor__n0001> is unconnected in block <comp>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <Mxor__n0001> is unconnected in block <comp>.
   It will be removed from the design.

Optimizing unit <step_motor_degree_forward_reverse_lcd> ...

Optimizing unit <bin_add_4bit> ...

Optimizing unit <bcd_add_sub_4dig> ...

Mapping all equations...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block step_motor_degree_forward_reverse_lcd, actual ratio is 6.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-5 

 Number of Slices:                     112  out of   2352     4%  
 Number of Slice Flip Flops:            60  out of   4704     1%  
 Number of 4 input LUTs:               207  out of   4704     4%  
 Number of bonded IOBs:                 17  out of    144    11%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
divider_15:q                       | NONE                   | 15    |
divider_25:q                       | NONE                   | 20    |
clk                                | BUFGP                  | 25    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 30.535ns (Maximum Frequency: 32.749MHz)
   Minimum input arrival time before clock: 32.117ns
   Maximum output required time after clock: 9.749ns
   Maximum combinational path delay: No path found

=========================================================================

Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -quiet -dd
c:\hardware\step_motor_degree_forward_reverse_lcd/_ngo -uc
STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCDCF.ucf -insert_keep_hierarchy -p
xc2s200-pq208-5 step_motor_degree_forward_reverse_lcd.ngc
step_motor_degree_forward_reverse_lcd.ngd 

Reading NGO file
"C:/HARDWARE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/step_motor_degree_forward_rev
erse_lcd.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file
"STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCDCF.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "step_motor_degree_forward_reverse_lcd.ngd" ...

Writing NGDBUILD log file "step_motor_degree_forward_reverse_lcd.bld"...

NGDBUILD done.

Completed process "Translate".



Started process "Map".

Using target part "2s200pq208-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
   Number of errors:      0
   Number of warnings:    0
   Number of Slices:                105 out of  2,352    4%
   Number of Slices containing
      unrelated logic:                0 out of    105    0%
   Number of Slice Flip Flops:       52 out of  4,704    1%
   Total Number 4 input LUTs:       191 out of  4,704    4%
      Number used as LUTs:                        173
      Number used as a route-thru:                 18
   Number of bonded IOBs:            17 out of    140   12%
      IOB Flip Flops:                               8
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%
Total equivalent gate count for design:  1,770
Additional JTAG gate count for IOBs:  864
Peak Memory Usage:  56 MB

Mapping completed.
See MAP report file "step_motor_degree_forward_reverse_lcd_map.mrp" for details.