📄 bcd_add_1dig.vhd
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--***************************************
--* 1 Digital BCD Adder *
--* Filename : BCD_ADD_1DIG.VHD *
--***************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.all;
entity BCD_ADD_1DIG is
Port ( CIN : in std_logic;
X : in std_logic_vector(3 downto 0);
Y : in std_logic_vector(3 downto 0);
SUM : out std_logic_vector(3 downto 0);
CARRY : out std_logic);
end BCD_ADD_1DIG;
architecture Behavioral of BCD_ADD_1DIG is
signal C_OUT : std_logic;
signal FLAG : std_logic;
signal SUM_BIN : std_logic_vector(3 downto 0);
signal COMPENSATION : std_logic_vector(3 downto 0);
begin
FLAG <= C_OUT or (SUM_BIN(1) and SUM_BIN(3)) or (SUM_BIN(2) and SUM_BIN(3));
COMPENSATION <= "0110" when FLAG = '1' else "0000";
CARRY <= FLAG;
BIN_ADD1: BIN_ADD_4BIT port map (CIN,X,Y,SUM_BIN,C_OUT);
BIN_ADD2: BIN_ADD_4BIT port map ('0',SUM_BIN,COMPENSATION,SUM);
end Behavioral;
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