step_motor_degree_forward_reverse_lcd.par

將正在順時針或逆時針旋轉的步進馬達目前角度顯示在ＬＣＭ上。

Release 6.1.03i Par G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

LIOU::  Tue Jan 06 12:45:35 2004


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1
step_motor_degree_forward_reverse_lcd_map.ncd
step_motor_degree_forward_reverse_lcd.ncd
step_motor_degree_forward_reverse_lcd.pcf 


Constraints file: step_motor_degree_forward_reverse_lcd.pcf

Loading device database for application Par from file
"step_motor_degree_forward_reverse_lcd_map.ncd".
   "step_motor_degree_forward_reverse_lcd" is an NCD, version 2.38, device
xc2s200, package pq208, speed -5
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-11-04.


Resolved that GCLKIOB <CLK> must be placed at site P80.
Resolved that IOB <LCM_DATA<4>> must be placed at site P200.
Resolved that IOB <LCM_DATA<5>> must be placed at site P201.
Resolved that IOB <LCM_DATA<6>> must be placed at site P202.
Resolved that IOB <RESET> must be placed at site P180.
Resolved that IOB <LCM_DATA<7>> must be placed at site P203.
Resolved that IOB <TRIGGER<0>> must be placed at site P22.
Resolved that IOB <LCM_RW> must be placed at site P191.
Resolved that IOB <TRIGGER<1>> must be placed at site P21.
Resolved that IOB <TRIGGER<2>> must be placed at site P20.
Resolved that IOB <TRIGGER<3>> must be placed at site P18.
Resolved that IOB <DIRECTION> must be placed at site P146.
Resolved that IOB <LCM_EN> must be placed at site P192.
Resolved that IOB <LCM_RS> must be placed at site P189.
Resolved that IOB <LCM_DATA<0>> must be placed at site P193.
Resolved that IOB <LCM_DATA<1>> must be placed at site P194.
Resolved that IOB <LCM_DATA<2>> must be placed at site P195.
Resolved that IOB <LCM_DATA<3>> must be placed at site P199.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            17 out of 140    12%
      Number of LOCed External IOBs   17 out of 17    100%

   Number of SLICEs                  111 out of 2352    4%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Phase 1.1
Phase 1.1 (Checksum:989937) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
.............
.............
Phase 5.8 (Checksum:9abcfc) REAL time: 3 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 3 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 3 secs 

Writing design to file step_motor_degree_forward_reverse_lcd.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 803 unrouted;       REAL time: 3 secs 

Phase 2: 773 unrouted;       REAL time: 3 secs 

Phase 3: 174 unrouted;       REAL time: 4 secs 

Phase 4: 174 unrouted; (0)      REAL time: 4 secs 

Phase 5: 174 unrouted; (0)      REAL time: 4 secs 

Phase 6: 174 unrouted; (0)      REAL time: 4 secs 

Phase 7: 0 unrouted; (0)      REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 3 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         CLK_BUFGP          |  Global  |   13   |  0.000     |  0.762      |
+----------------------------+----------+--------+------------+-------------+
|       DIVIDER<15>          |   Local  |   15   |  1.040     |  3.771      |
+----------------------------+----------+--------+------------+-------------+
|       DIVIDER<25>          |   Local  |   16   |  2.797     |  5.131      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 256


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.788
   The MAXIMUM PIN DELAY IS:                               5.507
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.882

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
         241         300         134          52          76           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_CLK = PERIOD TIMEGRP "CLK"  25 nS   HI | 25.000ns   | 6.010ns    | 13   
  GH 50.000000 %                            |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  57 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file step_motor_degree_forward_reverse_lcd.ncd.


PAR done.