complement.vhd

来自「將正在順時針或逆時針旋轉的步進馬達目前角度顯示在ＬＣＭ上。」· VHDL 代码 · 共 33 行

--*********************************
--*     9'Complement Generator    *
--*   Filename : COMPLEMENT.VHD   *
--*********************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity COMPLEMENT is
    Port ( ADD_SUB  : in std_logic;
           DATA_IN  : in std_logic_vector(3 downto 0);
           DATA_OUT : out std_logic_vector(3 downto 0));
end COMPLEMENT;

architecture Behavioral of COMPLEMENT is

begin
  process (DATA_IN,ADD_SUB)

    begin
      if ADD_SUB      = '1' then
         DATA_OUT(3) <= not (DATA_IN(3) or DATA_IN(2) or DATA_IN(1));
         DATA_OUT(2) <=	DATA_IN(2) xor DATA_IN(1);
	    DATA_OUT(1) <=	DATA_IN(1);
	    DATA_OUT(0) <=	not (DATA_IN(0));
      else
         DATA_OUT    <= DATA_IN;
      end if;
  end process;
end Behavioral;