step_motor_degree_forward_reverse_lcd.syr

將正在順時針或逆時針旋轉的步進馬達目前角度顯示在ＬＣＭ上。

Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 18

Macro Statistics :
# Registers                        : 20
#      1-bit register              : 17
#      16-bit register             : 1
#      25-bit register             : 1
#      6-bit register              : 1
# Multiplexers                     : 14
#      2-to-1 multiplexer          : 14
# Adders/Subtractors               : 2
#      25-bit adder                : 1
#      6-bit adder                 : 1
# Comparators                      : 1
#      6-bit comparator less       : 1
# Xors                             : 32
#      1-bit xor3                  : 32

Cell Usage :
# BELS                             : 279
#      GND                         : 1
#      LUT1                        : 32
#      LUT2                        : 19
#      LUT2_D                      : 1
#      LUT2_L                      : 4
#      LUT3                        : 27
#      LUT3_D                      : 3
#      LUT3_L                      : 6
#      LUT4                        : 86
#      LUT4_D                      : 11
#      LUT4_L                      : 27
#      MUXCY                       : 29
#      MUXF5                       : 3
#      VCC                         : 1
#      XORCY                       : 29
# FlipFlops/Latches                : 61
#      FDC                         : 59
#      FDP                         : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 17
#      IBUF                        : 2
#      OBUF                        : 15
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-5 

 Number of Slices:                     115  out of   2352     4%  
 Number of Slice Flip Flops:            61  out of   4704     1%  
 Number of 4 input LUTs:               216  out of   4704     4%  
 Number of bonded IOBs:                 17  out of    144    11%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
DIVIDER_25:Q                       | NONE                   | 19    |
CLK                                | BUFGP                  | 25    |
DIVIDER_15:Q                       | NONE                   | 17    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.616ns (Maximum Frequency: 64.037MHz)
   Minimum input arrival time before clock: 17.845ns
   Maximum output required time after clock: 9.949ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'DIVIDER_25:Q'
Delay:               15.616ns (Levels of Logic = 7)
  Source:            DEGREE_5 (FF)
  Destination:       DEGREE_13 (FF)
  Source Clock:      DIVIDER_25:Q rising
  Destination Clock: DIVIDER_25:Q rising

  Data Path: DEGREE_5 to DEGREE_13
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             11   1.292   2.300  DEGREE_5 (DEGREE_5)
     LUT2:I0->O            1   0.653   1.150  ADD_SUB_ADD_SUB2_BCD_ADD_BIN_ADD1__n00001_SW3_SW0 (N7519)
     LUT4_L:I3->LO         1   0.653   0.100  ADD_SUB_ADD_SUB2_BCD_ADD_BIN_ADD1__n00001_SW3 (N7274)
     LUT4:I0->O           14   0.653   2.600  ADD_SUB_ADD_SUB2_BCD_ADD_FLAG_SW112 (ADD_SUB_CT<2>)
     LUT4_D:I0->O          4   0.653   1.600  ADD_SUB_ADD_SUB4_BCD_ADD_FLAG_SW0 (N6066)
     LUT3_L:I2->LO         1   0.653   0.100  ADD_SUB_ADD_SUB4_BCD_ADD_FLAG_SW1_SW0 (N7515)
     LUT4:I1->O            1   0.653   1.150  ADD_SUB_ADD_SUB4_BCD_ADD_FLAG_SW1 (N7278)
     LUT4_L:I3->LO         1   0.653   0.000  _n0010<13>1 (_n0010<13>)
     FDC:D                     0.753          DEGREE_13
    ----------------------------------------
    Total                     15.616ns (6.616ns logic, 9.000ns route)
                                       (42.4% logic, 57.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK'
Delay:               7.532ns (Levels of Logic = 12)
  Source:            DIVIDER_15 (FF)
  Destination:       DIVIDER_25 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: DIVIDER_15 to DIVIDER_25
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             19   1.292   3.100  DIVIDER_15 (DIVIDER_15)
     LUT1:I0->O            1   0.653   0.000  LCM_EN_OBUF_rt (LCM_EN_OBUF_rt)
     MUXCY:S->O            1   0.784   0.000  DIVIDER_Madd__n0000_inst_cy_20 (DIVIDER_Madd__n0000_inst_cy_20)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_21 (DIVIDER_Madd__n0000_inst_cy_21)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_22 (DIVIDER_Madd__n0000_inst_cy_22)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_23 (DIVIDER_Madd__n0000_inst_cy_23)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_24 (DIVIDER_Madd__n0000_inst_cy_24)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_25 (DIVIDER_Madd__n0000_inst_cy_25)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_26 (DIVIDER_Madd__n0000_inst_cy_26)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_27 (DIVIDER_Madd__n0000_inst_cy_27)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_28 (DIVIDER_Madd__n0000_inst_cy_28)
     MUXCY:CI->O           0   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_29 (DIVIDER_Madd__n0000_inst_cy_29)
     XORCY:CI->O           1   0.500   0.000  DIVIDER_Madd__n0000_inst_sum_30 (DIVIDER__n0000<24>)
     FDC:D                     0.753          DIVIDER_25
    ----------------------------------------
    Total                      7.532ns (4.432ns logic, 3.100ns route)
                                       (58.8% logic, 41.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'DIVIDER_15:Q'
Delay:               12.820ns (Levels of Logic = 5)
  Source:            LCM_COUNT_2 (FF)
  Destination:       LCM_DATA_1 (FF)
  Source Clock:      DIVIDER_15:Q rising
  Destination Clock: DIVIDER_15:Q rising

  Data Path: LCM_COUNT_2 to LCM_DATA_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             22   1.292   3.300  LCM_COUNT_2 (LCM_COUNT_2)
     LUT3_D:I0->O          3   0.653   1.480  Ker42761 (N4278)
     LUT4:I0->O            3   0.653   1.480  _n00681 (_n0068)
     LUT4:I1->O            1   0.653   1.150  _n0008<1>39 (CHOICE315)
     LUT4_L:I3->LO         1   0.653   0.100  _n0008<1>60 (CHOICE317)
     LUT4_L:I2->LO         1   0.653   0.000  _n0008<1>70 (_n0008<1>)
     FDC:D                     0.753          LCM_DATA_1
    ----------------------------------------
    Total                     12.820ns (5.310ns logic, 7.510ns route)
                                       (41.4% logic, 58.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'DIVIDER_25:Q'
Offset:              17.845ns (Levels of Logic = 7)
  Source:            DIRECTION (PAD)
  Destination:       DEGREE_13 (FF)
  Destination Clock: DIVIDER_25:Q rising

  Data Path: DIRECTION to DEGREE_13
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            55   0.924   4.950  DIRECTION_IBUF (DIRECTION_IBUF)
     LUT4_D:I3->O          6   0.653   1.850  ADD_SUB_ADD_SUB1_BCD_ADD_FLAG (ADD_SUB_CT<1>)
     LUT4:I1->O           14   0.653   2.600  ADD_SUB_ADD_SUB2_BCD_ADD_FLAG_SW112 (ADD_SUB_CT<2>)
     LUT4_D:I0->O          4   0.653   1.600  ADD_SUB_ADD_SUB4_BCD_ADD_FLAG_SW0 (N6066)
     LUT3_L:I2->LO         1   0.653   0.100  ADD_SUB_ADD_SUB4_BCD_ADD_FLAG_SW1_SW0 (N7515)
     LUT4:I1->O            1   0.653   1.150  ADD_SUB_ADD_SUB4_BCD_ADD_FLAG_SW1 (N7278)
     LUT4_L:I3->LO         1   0.653   0.000  _n0010<13>1 (_n0010<13>)
     FDC:D                     0.753          DEGREE_13
    ----------------------------------------
    Total                     17.845ns (5.595ns logic, 12.250ns route)
                                       (31.4% logic, 68.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'DIVIDER_15:Q'
Offset:              8.189ns (Levels of Logic = 1)
  Source:            LCM_RS (FF)
  Destination:       LCM_RS (PAD)
  Source Clock:      DIVIDER_15:Q rising

  Data Path: LCM_RS to LCM_RS
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   1.292   1.340  LCM_RS (LCM_RS_OBUF)
     OBUF:I->O                 5.557          LCM_RS_OBUF (LCM_RS)
    ----------------------------------------
    Total                      8.189ns (6.849ns logic, 1.340ns route)
                                       (83.6% logic, 16.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Offset:              9.949ns (Levels of Logic = 1)
  Source:            DIVIDER_15 (FF)
  Destination:       LCM_EN (PAD)
  Source Clock:      CLK rising

  Data Path: DIVIDER_15 to LCM_EN
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             19   1.292   3.100  DIVIDER_15 (DIVIDER_15)
     OBUF:I->O                 5.557          LCM_EN_OBUF (LCM_EN)
    ----------------------------------------
    Total                      9.949ns (6.849ns logic, 3.100ns route)
                                       (68.8% logic, 31.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'DIVIDER_25:Q'
Offset:              8.329ns (Levels of Logic = 1)
  Source:            PATTERN_3 (FF)
  Destination:       TRIGGER<3> (PAD)
  Source Clock:      DIVIDER_25:Q rising

  Data Path: PATTERN_3 to TRIGGER<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              3   1.292   1.480  PATTERN_3 (PATTERN_3)
     OBUF:I->O                 5.557          TRIGGER_3_OBUF (TRIGGER<3>)
    ----------------------------------------
    Total                      8.329ns (6.849ns logic, 1.480ns route)
                                       (82.2% logic, 17.8% route)

=========================================================================
CPU : 9.40 / 10.04 s | Elapsed : 9.00 / 10.00 s
 
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Total memory usage is 63212 kilobytes